AD9707 Analog Devices, AD9707 Datasheet - Page 32

• Manufacturer Part Number: AD9707
• Manufacturer: Analog Devices

Specifications of AD9707

• Resolution (bits): 14bit
• Dac Update Rate: 175MSPS
• Dac Settling Time: 11ns
• Max Pos Supply (v): +3.6V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

AD9704/AD9705/AD9706/AD9707
SPI REGISTER MAP
Table 15.
Mnemonic
SPI CTL
Data
Version
CALMEM
MEMRDWR
MEMADDR
MEMDATA
SCLK
SDIO
SCLK
SDO
CSB
SDIO
SCLK
SDIO
CSB
CSB
Figure 72. Serial Register Interface Timing, MSB First Write
Figure 73. Serial Register Interface Timing, MSB First Read
Figure 74. Serial Register Interface Timing, LSB First Write
R/W N1 N0 A4 A3
A0
R/W N1 N0 A4 A3
Addr
0x00
0x02
0x0D
0x0E
0x0F
0x10
0x11
INSTRUCTION CYCLE
INSTRUCTION CYCLE
A1 A2 A3
INSTRUCTION CYCLE
Bit 7
SDIODIR
DATAFMT
CALSTAT
A4 N0
A2 A1 A0
A2 A1 A0 D7
N1 R/W D0
D7
Bit 6
DATADIR
CALEN
0
D6
DATA TRANSFER CYCLE
N
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
D1
D6
N
0
D5
N
D2
D5
N
0
N
Bit 5
SWRST
CALMEM[1]
MEMADDR[5]
MEMDATA[5]
D3
D4
D3
0
N
0
D2
D5
D2
0
N
0
D1
D6
D1
0
N
0
D0
D7
D0
0
N
0
Rev. B | Page 32 of 44
Bit 4
LNGINS
DCLKPOL
CALMEM[0]
MEMADDR[4]
MEMDATA[4]
SCLK
SCLK
SCLK
SDIO
SDIO
SDIO
CSB
CSB
SDO
CSB
PDN
DESKEW
SMEMWR
Bit 3
VER[3]
MEMADDR[3]
MEMDATA[3]
I1
Figure 75. Serial Register Interface Timing, LSB First Read
A0 A1 A2 A3 A4 N0 N1 R/W
Figure 76. Timing Diagram for SPI Register Write
Figure 77. Timing Diagram for SPI Register Read
I0
INSTRUCTION BIT 7
INSTRUCTION CYCLE
t
t
DS
DS
Bit 2
Sleep
CLKDIFF
VER[2]
DIVSEL[2]
SMEMRD
MEMADDR[2]
MEMDATA[2]
t
PWH
t
DH
t
D7
SCLK
t
PWL
INSTRUCTION BIT 6
D0
Bit 1
CLKOFF
VER[1]
DIVSEL[1]
MEMADDR[1]
MEMDATA[1]
t
D1
SU
DATA TRANSFER CYCLE
0
D2
D6
0
D4
Data Sheet
t
N
HLD
D5
N
Bit 0
EXREF
CALCLK
VER[0]
DIVSEL[0]
UNCAL
MEMADDR[0]
MEMDATA[0]
D6
N
D7
D5
N