AD5667 Analog Devices, AD5667 Datasheet - Page 25

• Manufacturer Part Number: AD5667
• Manufacturer: Analog Devices

Specifications of AD5667

• Resolution (bits): 16bit
• Dac Update Rate: 250kSPS
• Dac Settling Time: 4µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser

Synchronous LDAC
The DAC registers are updated after new data is read in. LDAC
can be permanently low or pulsed.
Asynchronous LDAC
The outputs are not updated at the same time that the input
registers are written to. When LDAC goes low, the DAC
registers are updated with the contents of the input register.
The LDAC register gives the user full flexibility and control over
the hardware LDAC pin. This register allows the user to select
which combination of channels to simultaneously update when
the hardware LDAC pin is executed. Setting the LDAC bit
register to 0 for a DAC channel means that the update of this
channel is controlled by the LDAC pin. If this bit is set to 1, this
channel synchronously updates, that is, the DAC register is
updated after new data is read in, regardless of the state of the
LDAC pin. It effectively sees the LDAC pin as being pulled low.
See Table 10 for the LDAC register mode of operation. This
flexibility is useful in applications when the user wants to
simultaneously update select channels while the rest of the
channels are synchronously updating.
Writing to the DAC using Command 110 loads the 2-bit LDAC
register [DB1:DB0]. The default for each channel is 0, that is,
the LDAC pin works normally. Setting the bits to 1 means the
DAC register is updated, regardless of the state of the LDAC
pin. See Figure 63 for contents of the input shift register during
the LDAC register setup command.
Table 10. LDAC Register Mode of Operation:
Load DAC Register
LDAC Bits
(DB1 to DB0)
0
1
POWER-DOWN MODES
Command 100 is reserved for the power-up/down function.
The power-up/down modes are programmed by setting Bit
DB5 and Bit DB4. This defines the output state of the DAC
R
0
S
X
C2
1
COMMAND
LDAC Pin
1/0
x = don’t care
C1
1
C0
0
A2
A2
DAC ADDRESS
(DON’T CARE)
LDAC Operation
Determined by LDAC pin.
The DAC registers are updated
after new data is read in.
A1
A1
A0
A0
DB15 DB14 DB13 DB12 DB11 DB10
X
X
Figure 63. LDAC Setup Command
X
Rev. 0 | Page 25 of 32
DON’T CARE
X
AD5627R/AD5647R/AD5667R, AD5627/AD5667
X
X
amplifier, as shown in Table 11. Bit DB1and Bit DB0 determine
to which DAC or DACs the power-up/down command is
applied. Setting one of these bits to 1 applies the power-up/down
state defined by DB5 and DB4 to the corresponding DAC. If a
bit is 0, the state of the DAC is unchanged. Figure 65 shows the
contents of the input shift register for the power up/down
command.
When Bit DB5 and Bit DB4 are set to 0, the part works normally
with its normal power consumption of 400 μA at 5 V. However,
for the three power-down modes, the supply current falls to
480 nA at 5 V. Not only does the supply current fall, but the
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This allows the
output impedance of the part to be known while the part is in
power-down mode. The outputs can either be connected
internally to GND through a 1 kΩ or 100 kΩ resistor, or left
open-circuited (three-state) as shown in Figure 62.
Table 11. Modes of Operation for the AD56x7R/AD56x7
DB5
0
0
1
1
The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shut down when power-
down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit
power-down is typically 4 μs for V
DB9
X
STRING DAC
RESISTOR
DB8
X
DB4
0
1
0
1
Figure 62. Output Stage During Power-Down
DB7
X
DB6
X
Operating Mode
Normal operation
Power-down modes
1 kΩ pull-down to GND
100 kΩ pull-down to GND
Three-state, high impedance
POWER-DOWN
AMPLIFIER
CIRCUITRY
DON’T CARE
DB5
X
DB4
X
DD
DB3
= 5 V.
X
DB2
(0 = LDAC PIN ENABLED)
NETWORK
RESISTOR
X
DACB DACA
DAC SELECT
DB1
V
OUT
DB0