AD5371 Analog Devices, AD5371 Datasheet - Page 12

• Manufacturer Part Number: AD5371
• Description: 40-Channel, 14-Bit, Serial Input, Voltage Output DAC
• Manufacturer: Analog Devices

Specifications of AD5371

• Resolution (bits): 14bit
• Dac Update Rate: 540kSPS
• Dac Settling Time: 20µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5371
Pin No.
58
31
41
7
16
52
21
50
19, 44
20, 45
64, 76
65, 75
66
67
68
69
70
71
72
74
77
22 to 24,
35, 42,
43, 51,
53, 59
Ball No.
D11
L7
L12
F1
L3
G12
M4
H11
J5 to J9, L11,
M12
E4, F4, G4, H4,
J4, L2, M1
A11, A12
A10, B10
A9
B9
A8
B8
A7
B7
A6
B5
A1, B1, C1, C2,
D4 to D9, E9,
F9, G9, H9
A2, B6, F2, F11,
G1, G11
VREF2
DGND
Mnemonic
SIGGND0
SIGGND1
SIGGND2
SIGGND3
SIGGND4
VREF0
VREF1
V
V
DV
SYNC
SYNC
SCLK
SCLK
SDI
SDI
SPI/LVDS
SDO
AGND
NC
DD
SS
CC
Description
Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to this voltage.
Reference Ground for DAC 8 to DAC 15. VOUT8 to VOUT15 are referenced to this voltage.
Reference Ground for DAC 16 to DAC 23. VOUT16 to VOUT23 are referenced to this voltage.
Reference Ground for DAC 24 to DAC 31. VOUT24 to VOUT31 are referenced to this voltage.
Reference Ground for DAC 32 to DAC 39. VOUT32 to VOUT39 are referenced to this voltage.
Reference Input for DAC 0 to DAC 7. This reference voltage is referred to AGND.
Reference Input for DAC 8 to DAC 15. This reference voltage is referred to AGND.
Reference Input for DAC 16 to DAC 39. This reference voltage is referred to AGND.
Positive Analog Power Supply; 9 V to 16.5 V for specified performance. Decouple these pins
with 0.1 μF ceramic capacitors and 10 μF capacitors.
Negative Analog Power Supply; −16.5 V to −8 V for specified performance. Decouple these
pins with 0.1 μF ceramic capacitors and 10 μF capacitors.
Ground for All Digital Circuitry. Connect both DGND pins to the DGND plane.
Logic Power Supply; 2.5 V to 5.5 V. Decouple these pins with 0.1 μF ceramic capacitors and
10 μF capacitors.
Active Low or Differential SYNC Input (Complement) for SPI or LVDS Interface. This is the
frame synchronization signal for the SPI or LVDS serial interface. See the Timing Characteristics
section for more details.
Differential SYNC Input for LVDS Interface. This is the frame synchronization signal for the
LVDS serial interface. See the Timing Characteristics section for more details.
Serial Clock Input for SPI or LVDS Interface. See the Timing Characteristics section for more
details.
Differential Serial Clock Input (Complement) for LVDS Interface. See the Timing Characteristics
section for more details.
Serial Data Input for SPI or LVDS Interface. See the Timing Characteristics section for more
details.
Differential Serial Data Input (Complement) for LVDS Interface. See the Timing Characteristics
section for more details.
Interface Selection Pin. If the pin is low, the SPI interface is selected. If the pin is high, the
LVDS interface is selected.
Serial Data Output for SPI Interface. CMOS output. SDO can be used for readback. Data is
clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK.
Ground for All Analog Circuitry. Connect the AGND pin to the AGND plane.
No Connect. Do not connect these pins.
Rev. B | Page 12 of 28