AD5441 Analog Devices, AD5441 Datasheet - Page 12

• Manufacturer Part Number: AD5441
• Description: 12-Bit Serial Input Multiplying DAC
• Manufacturer: Analog Devices

Specifications of AD5441

• Resolution (bits): 12bit
• Dac Update Rate: 5MSPS
• Dac Settling Time: 500ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Ser

AD5441
BIPOLAR 4-QUADRANT MULTIPLYING
Figure 24 shows a suggested circuit to achieve 4-quadrant
multiplying operation. The summing amplifier multiplies V
by 2 and offsets the output with the reference voltage so that a
midscale digital input code of 2048 places V
full-scale voltage is V
The positive full-scale output is −(V
is loaded with all ones. Therefore, the digital coding is offset
binary. The voltage output transfer equation for various input
data and reference (or signal) values follows
where:
D is the decimal data loaded into the DAC register.
V
INTERFACE LOGIC INFORMATION
The AD5441 has been designed for ease of operation. The
timing diagram in Figure 2 illustrates the input register loading
sequence. Note that the most significant bit (MSB) is loaded
first. Once the 12-bit input register is full, the data is transferred
to the DAC register by taking LD momentarily low.
REF
is the externally applied reference voltage source.
V
OUT2
= (D/2048 − 1) − V
REF
when the DAC is loaded with all zeros.
V
±10V
NOTES
1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
REF
ADJUST R1 FOR V
R3 AND R4.
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
REF
R1
REF
− 1 LSB) when the DAC
V
REF
LD
OUT
V
V
µCONTROLLER
DD
DD
OUT2
= 0V WITH CODE 10000000 LOADED TO DAC.
CLK
AD5441
at 0 V. The negative
SRI
Figure 24. Bipolar (4-Quadrant) Operation
R
FB
I
GND
OUT
20kΩ
OUT1
R3
R2
Rev. A | Page 12 of 16
1
AGND
C1
A1
DIGITAL SECTION
The digital inputs of the AD5441, SRI, LD , and CLK, are TTL-
compatible. The input voltage levels affect the amount of current
drawn from the supply; peak supply current occurs as the digital
input (V
for the supply current vs. logic input voltage graph. Maintaining
the digital input voltage levels as close as possible to the supplies,
V
digital inputs of the AD5441 were designed with ESD resistance
incorporated through careful layout and the inclusion of input
protection circuitry.
and series resistor; this input structure is duplicated on each
digital input. High voltage static charges applied to the inputs
are shunted to the supply and ground rails through forward-
biased diodes. These protection diodes were designed to clamp
the inputs to well below dangerous levels during static discharge
conditions.
DD
and GND, minimizes supply current consumption. The
10kΩ
R4
IN
LD, CLK, SRI
) passes through the transition region. See
20kΩ
A2
R5
GND
V
DD
Figure 23. Digital Input Protection
Figure 23
V
OUT
5kΩ
= –V
shows the input protection diodes
REF
TO +V
REF
Figure 15