AD5064 Analog Devices, AD5064 Datasheet
AD5064
Specifications of AD5064
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AD5064 Summary of contents
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... Trademarks and registered trademarks are the property of their respective owners. Fully Accurate, 12-/14-/16-Bit V SPI Interface TSSOP AD5064-1 AD5666 SCLK SYNC DIN SDO Figure 1. AD5064-1 Functional Equivalent and Pin Compatible with AD5666 AD5024/ AD5044/ AD5064 SCLK SYNC DIN Figure 2. AD5024/AD5044/AD5064 with Individual Reference Pins PRODUCT HIGHLIGHTS are low power, quad 1 ...
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... Power Supply Bypassing and Grounding................................ 24 Microprocessor Interfacing....................................................... 25 Applications Information .............................................................. 26 Using a Reference as a Power Supply....................................... 26 Bipolar Operation....................................................................... 26 Using the AD5024/AD5044/AD5064/AD5064-1 with a Galvanically Isolated Interface ................................................. 26 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 28 Changes to Figure 4...........................................................................6 Added Figure 6...................................................................................8 Added Table 6 ...
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... Rev Page AD5024/AD5044/AD5064 , unless otherwise specified. All specifications T Unit Conditions/Comments Max Bits AD5064/AD5064-1 Bits AD5044 Bits AD5024 ±4 LSB AD5064/AD5064- +105°C ±4 LSB AD5064/AD5064- +125°C LSB AD5044 LSB AD5024 ±1 LSB ± 2 5.5 V REF DD ±1.8 mV μV/°C ± ...
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... AD5024: Code 32 to Code 4064. Output unloaded. 4 See the Terminology section. 5 Offset error calculated using a reduced code range—AD5064/AD5064-1: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to Code 4064. Output unloaded 6 Guaranteed by design and characterization; not production tested. ...
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... Daisy-chain mode only. 3 Measured with the load circuit of Figure 3. t determines the maximum SCLK frequency in daisy-chain mode. AD5064-1 only Time to exit power-down mode to normal mode of AD5024/AD5044/AD5064/AD5064-1, 32 Circuit and Timing Diagrams = 1 ns/V (10 and timed from a voltage level unless otherwise noted ...
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... AD5024/AD5044/AD5064 SCLK t 8 SYNC DIN DB31 1 LDAC 2 LDAC CLR V OUT 1 ASYNCHRONOUS LDAC UPDATE MODE. 2 SYNCHRONOUS LDAC UPDATE MODE. SCLK SYNC DIN DB31 INPUT WORD FOR DAC N SDO 1 LDAC CLR DAISY-CHAIN MODE, LDAC MUST BE USED ASYNCHRONOUSLY ...
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... Exposure to absolute + 0 maximum rating conditions for extended periods may affect + 0 device reliability ESD CAUTION − T )/θ J MAX A JA Rev Page AD5024/AD5044/AD5064 ...
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... This is a common pin for reference input for DAC A, DAC B, DAC C, and DAC D. REFIN 8 SDO Serial Data Output. Can be used to daisy-chain a number of AD5064-1 devices together. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. 9 CLR Asynchronous Clear Input ...
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... REF OUT REF TOP VIEW (Not to Scale REF OUT CLR OUT POR REF Figure 7. 16-Lead TSSOP (RU-16) Pin Configuration Rev Page AD5024/AD5044/AD5064 Figure 4 . Pulsing nd falling edge, the rising edge of powers up the DD ...
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... Rev Page 4.096V REF T = 25° 512 16,640 32,768 48,896 DAC CODE Figure 11. AD5064/AD5064-1 DNL 4.096V REF T = 25° 4096 8192 12,288 DAC CODE Figure 12. AD5044 DNL 4.096V ...
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... Rev Page AD5024/AD5044/AD5064 T = 25°C A MAX TUE @ V = 5.5V DD MIN TUE @ V = 5.5V DD 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) Figure 17. TUE vs. Reference Input Voltage DAC A DAC B DAC D DAC 5. 4.096V REF – ...
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... AD5024/AD5044/AD5064 0 4.096V REF T = 25°C A 0.1 GAIN ERROR 0 FULL-SCALE ERROR –0.1 –0.2 4.50 4.75 5.00 V (V) DD Figure 20. Gain Error and Full-Scale Error vs. Supply Voltage 0. 4.096V REF T = 25°C A 0.09 0.06 0.03 0 4.50 4.75 5.00 V (V) DD Figure 21. Offset Error Voltage vs. Supply Voltage 40 MEAN: 4.11699 SD: 0.0544403 35 LIMITS: LOW: 3 HIGH: 4.3 CPk: LOW: 6.84 HIGH: 1. ...
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... CH2 = CH1 DAC A –1 –2 –3 0 2.52V Rev Page AD5024/AD5044/AD5064 = 4.096V V DD DAC A CH3 2V M2ms A CH1 2.52V T 20.4% Figure 29. Power-On Reset to Midscale OUT DD POWER-UP TO MIDSCALE OUTPUT UNLOADED CH2 500mV M2µs A CH2 T 55% Figure 30 ...
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... AD5024/AD5044/AD5064 5V 4.096V DD REF 25º –1 –2 –3 –4 0 2.5 5.0 TIME (μs) Figure 32. Analog Crosstalk –1 –2 –3 –4 0 2.5 5.0 TIME (μs) Figure 33. DAC-to-DAC Crosstalk 4.096V DD REF T = 25ºC A DAC LOADED WITH MIDSCALE 4s/DIV Figure 34 ...
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... CH1 Figure 42. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale CH1 Figure 43. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale, Rev Page AD5024/AD5044/AD5064 CODE = MIDSCALE 4.096V DD REF –20 –15 –10 – ...
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... AD5024/AD5044/AD5064 V = 5V,V = 4.096V DD REF T = 25°C A CH1 20mV CH2 5V M4µs T 8.6% Figure 44. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, No Load DAC A 129mV p-p SCLK A CH2 1.2V Figure 45. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, Rev Page 25° 5V ...
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... OUT OUT region of the transfer function. Offset error is calculated using a reduced code range—AD5064/AD5604-1: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to Code 4064, with output unloaded. Offset error can be negative or positive and is expressed in millivolts. ...
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... AD5024/AD5044/AD5064 DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk measured by loading one of the DACs with a full-scale code change (all 0s to all 1s or vice versa) with LDAC low and monitoring the output of another DAC ...
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... The AD5064-1 model (see the Ordering Guide 16-bit, serial input, voltage output DAC that is identical to other AD5064 models but with a single reference pin for all DACs. The parts operate from supply voltages of 4 5.5 V. Data is written to the AD5024/AD5044/AD5064/AD5064 32-bit word format via a 3-wire serial interface ...
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... A0 D13 D12 D11 D10 DATA BITS Figure 48. AD5044 Shift Register Content D15 D14 D13 D12 D11 D10 D9 Figure 49. AD5064/AD5064-1 Shift Register Content DB0 VALID WRITE SEQUENCE, OUTPUT UPDATES Figure 50. SYNC Interrupt Facility Rev Page ...
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... DIN line is clocked into the 32-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50 MHz, making the AD5024/AD5044/AD5064/AD5064-1 compatible with high speed DSPs. On the 32 the last data bit is clocked in and the programmed function is executed, that is, an LDAC -dependent change in DAC register contents and/or a change in the mode of operation ...
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... CLR during power-on reset are ignored. The power-on reset circuit is triggered when V passes 2.6 V approximately and DD takes 50 μs to complete. No writes to the AD5024/AD5044/ AD5064/AD5064-1 should take place during this time. For applications which have a slow V ramp time (for example, DD more than 3ms recommended that a software reset command is written when the power supplies have reached their final value ...
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... CLEAR CODE REGISTER The AD5024/AD5044/AD5064/AD5064-1 have a hardware CLR pin that is an asynchronous clear input. The CLR input is falling edge sensitive. Bringing the CLR line low clears the contents of the input register and the DAC registers to the data contained in the user-configurable CLR register and sets the ...
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... When accuracy is important in a circuit helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board (PCB) containing the AD5024/AD5044/ AD5064/AD5064-1 should have separate analog and digital sections. If the AD5024/AD5044/AD5064/AD5064-1 are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only ...
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... Data is transmitted MSB first. To load data to the AD5024/AD5044/ AD5064, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. ...
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... SCLK INTERFACE AD5064/ DIN AD5064-1 Figure 56. REF195 as Power Supply to the AD5024/AD5044/AD5064/AD5064-1 BIPOLAR OPERATION The AD5024/AD5044/AD5064/AD5064-1 have been designed for single-supply operation, but a bipolar output range is also possible using the circuit shown in Figure 57. The circuit gives an output voltage range of ±5 V. Rail-to-rail operation at the ...
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... Figure 59. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 5.10 5.00 4. 4.50 6.40 4.40 BSC 4. PIN 1 1.20 MAX 0.20 0.09 8° 0.30 0.65 0° 0.19 SEATING BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 60. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev Page AD5024/AD5044/AD5064 0.75 0.60 0.45 0.75 0.60 0.45 ...
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... AD5064ARUZ-1REEL7 −40°C to +125°C AD5064BRUZ-1 −40°C to +125°C AD5064BRUZ-1REEL7 −40°C to +125°C AD5064BRUZ −40°C to +125°C AD5064BRUZ-REEL7 −40°C to +125°C AD5044BRUZ −40°C to +125°C AD5044BRUZ-REEL7 −40°C to +125°C AD5024BRUZ −40°C to +125°C AD5024BRUZ-REEL7 − ...