AD5752R Analog Devices, AD5752R Datasheet - Page 28
![no-image](/images/manufacturer_photos/0/0/56/analog_devices_sml.jpg)
AD5752R
Manufacturer Part Number
AD5752R
Description
Complete, Dual, 16-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DAC
Manufacturer
Analog Devices
Datasheet
1.AD5722R.pdf
(32 pages)
Specifications of AD5752R
Resolution (bits)
16bit
Dac Update Rate
1.07MSPS
Dac Settling Time
7.5µs
Max Pos Supply (v)
+16.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
Ser,SPI
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD5752RBREZ
Manufacturer:
AD
Quantity:
19 820
Part Number:
AD5752RBREZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD5722R/AD5732R/AD5752R
CONTROL REGISTER
The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the
control function selected. The control register options are shown in Table 24 and Table 25.
Table 24. Programming the Control Register
MSB
R/W
0
0
0
0
Table 25. Explanation of Control Register Options
Option
NOP
Clear
Load
SDO Disable
CLR Select
Clamp Enable
TSD Enable
Table 26. CLR Select Options
CLR Select Setting
0
1
POWER CONTROL REGISTER
The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the power
and thermal status of the AD5722R/AD5732R/AD5752R. The power control register options are shown in Table 27 and Table 28.
Table 27. Programming the Power Control Register
MSB
0
Table 28. Power Control Register Functions
Option
PU
PU
PU
TSD
OC
OC
R/ W
A
B
REF
A
B
Zero
0
Zero
0
0
0
0
Description
DAC A power-up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down
mode (default). After setting this bit to power DAC A, a power-up time of 10 μs is required. During this power-up time the DAC
register should not be loaded to the DAC output (see the Load DAC (LDAC) section). If the clamp enable bit of the control register
is cleared, DAC A powers down automatically on detection of an overcurrent, and PU
DAC B power-up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down
mode (default). After setting this bit to power DAC B, a power-up time of 10 μs is required. During this power-up time the DAC
register should not be loaded to the DAC output (see the Load DAC (LDAC) section). If the clamp enable bit of the control register
is cleared, DAC B powers down automatically on detection of an overcurrent, and PU
Reference power-up. When set, this bit places the internal reference in normal operating mode. When cleared, this bit places the
internal reference in power-down mode (default).
Thermal shutdown alert. Read-only bit. In the event of an overtemperature situation, both DACs are powered down and this bit is set.
DAC A overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC A, this bit is set.
DAC B overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC B, this bit is set.
REG2
0
REG2
0
0
0
0
REG1
1
No operation instruction used in readback operations.
Description
Addressing this function sets the DAC registers to the clear code and updates the outputs.
Addressing this function updates the DAC registers and, consequently, the DAC outputs.
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
See Table 26 for a description of the CLR select operation.
Set by the user to enable the current limit clamp. The channel does not power down upon detection of an
overcurrent; the current is clamped at 20 mA (default).
Cleared by the user to disable the current-limit clamp. The channel powers down upon detection of an overcurrent.
Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown
feature (default).
REG1
1
1
1
1
Unipolar Output Range
0 V
Midscale
REG0
0
REG0
1
1
1
1
A2
0
A2
0
0
1
1
A1
0
A1
0
0
0
0
A0
0
A0
0
1
0
1
DB15
to
DB11
X
DB15 to DB4
Don’t care
Rev. D | Page 28 of 32
DB10
X
DB9
OC
Output CLR Value
B
DB3
TSD enable
DB8
X
DB7
OC
Bipolar Output Range
0 V
Negative full scale
Clear, data = don’t care
Load, data = don’t care
NOP, data = don’t care
A
DB2
Clamp enable
DB6
0
B
A
is cleared to reflect this.
is cleared to reflect this.
DB5
TSD
DB4
PU
REF
DB1
CLR select
DB3
X
DB2
PU
B
DB0
LSB
SDO disable
DB1
X
LSB
DB0
PU
A