AD5422 Analog Devices, AD5422 Datasheet - Page 32

• Manufacturer Part Number: AD5422
• Description: Single Channel, 16-Bit, Serial Input, Current Source & Voltage Output DAC
• Manufacturer: Analog Devices

Specifications of AD5422

• Resolution (bits): 16bit
• Dac Update Rate: 40kSPS
• Dac Settling Time: 18µs
• Max Pos Supply (v): +40V
• Single-supply: No
• Dac Type: I or V Out
• Dac Input Format: SPI

AD5412/AD5422
DIGITAL POWER SUPPLY
By default, the DV
5.5 V. Alternatively, via the DV
power supply can be output on the DV
power supply for other devices in the system or as a termination
for pull-up resistors. This facility offers the advantage of not
having to bring a digital supply across an isolation barrier. The
internal power supply is enabled by leaving the DV
pin unconnected. To disable the internal supply, tie DV
SELECT to 0 V. DV
current (for a load regulation graph, see Figure 10).
EXTERNAL BOOST FUNCTION
The addition of an external boost transistor, as shown in
Figure 67, reduces the power dissipated in the AD5412/AD5422
by reducing the current flowing in the on-chip output transistor
(dividing it by the current gain of the external circuit). A
discrete NPN transistor with a breakdown voltage, BV
greater than 40 V can be used. The external boost capability
has been developed for users who may wish to use the
AD5412/AD5422 at the extremes of the supply voltage, load
current, and temperature range. The boost transistor can also
be used to reduce the amount of temperature-induced drift in
the part. This minimizes the temperature-induced drift of the
on-chip voltage reference, which improves on drift and
linearity.
EXTERNAL COMPENSATION CAPACITOR
The voltage output can ordinarily drive capacitive loads of up to
20 nF; if there is a requirement to drive greater capacitive loads,
of up to 1 µF, an external compensation capacitor can be con-
nected between the C
capacitor keeps the output voltage stable but also reduces the
bandwidth and increases the settling time of the voltage output.
DIGITAL SLEW RATE CONTROL
The slew rate control feature of the AD5412/AD5422 allows the
user to control the rate at which the output voltage or current
changes. With the slew rate control feature disabled, the output
changes at a rate limited by the output drive circuitry and the
attached load. See Figure 62 for current output step and
Figure 36 for voltage output step. To reduce the slew rate, enable
the slew rate control feature. With the feature enabled via the
SREN bit of the control register (see Table 14), the output, instead
of slewing directly between two values, steps digitally at a rate
defined by two parameters accessible via the control register, as
shown in Table 14. The parameters are set by the SR clock and
Figure 67. External Boost Configuration
AD5412/
AD5422
CC
CC
pin accepts a power supply of 2.7 V to
COMP
is capable of supplying up to 5 mA of
BOOST
I
0.022µF
OUT
and V
CC
OUT
SELECT pin, an internal 4.5 V
1kΩ
pins. The addition of the
CC
MJD31C
OR
PBSS8110Z
pin for use as a digital
R
LOAD
CC
SELECT
CEO
CC
,
Rev. D | Page 32 of 40
SR step bits. SR clock defines the rate at which the digital slew is
updated; SR step defines by how much the output value changes
at each update. Both parameters together define the rate of
change of the output voltage or current. Table 22 and Table 23
outline the range of values for both the SR clock and SR step
parameters. Figure 68 shows the output current changing for
ramp times of 10 ms, 50 ms, and 100 ms.
Table 22. Slew Rate Step Size Options
SR Step
000
001
010
011
100
101
110
111
Table 23. Slew Rate Update Clock Options
SR Clock
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
The time it takes for the output to slew over a given output
range can be expressed as follows:
where:
Slew Time is expressed in seconds.
Output Change is expressed in amps for I
When the slew rate control feature is enabled, all output
changes change at the programmed slew rate; if the CLEAR
pin is asserted, the output slews to the zero-scale value at the
programmed slew rate. The output can be halted at its current
value with a write to the control register. To avoid halting the
output slew, the slew active bit (see Table 19) can be read to
check that the slew has completed before writing to any of the
Slew
Time
=
Step
Size
Update Clock Frequency (Hz)
257,730
198,410
152,440
131,580
115,740
69,440
37,590
25,770
20,160
16,030
10,290
8280
6900
5530
4240
3300
AD5412 Step Size
(LSB)
1/16
1/8
1/4
1/2
1
2
4
8
×
Update
Output
Clock
Change
Frequency
OUT
or volts for V
AD5422 Step
Size (LSB)
1
2
4
8
16
32
64
128
×
LSB
Size
OUT
.
(1)