AD9148 Analog Devices, AD9148 Datasheet - Page 23

• Manufacturer Part Number: AD9148
• Manufacturer: Analog Devices

Specifications of AD9148

• Resolution (bits): 16bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Data Sheet
SPI OPTIONS
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by the LSB first bit
(Register 0x00, Bit 6). The default is MSB first (LSB first = 0).
When LSB first = 0 (MSB first), the instruction and data bit must
be written from MSB to LSB. Multibyte data transfers in MSB-
first format start with an instruction byte that includes the register
address of the most significant data byte. Subsequent data bytes
should follow from the high address to the low address. In MSB-
first mode, the serial port internal byte address generator decrements
for each data byte of the multibyte communication cycle.
When LSB first = 1 (LSB first), the instruction and data bit must
be written from LSB to MSB. Multibyte data transfers in LSB-
first format start with an instruction byte that includes the register
address of the least significant data byte followed by multiple data
bytes. The serial port internal byte address generator increments
for each byte of the multibyte communication cycle.
The serial port controller data address decrements from the data
address written toward 0x00 for multibyte I/O operations if the
MSB-first mode is active. The serial port controller address
increments from the data address written toward 0x1F for
multibyte I/O operations if the LSB-first mode is active.
SCLK
SDIO
SDO
CS
R/W A6 A5
Figure 41. Serial Register Interface Timing MSB First
INSTRUCTION CYCLE
A4 A3
A2 A1
A0 D7 D6
D7 D6
DATA TRANSFER CYCLE
N
N
D5
D5
N
N
D3
D3
0
0
D2
D2
0
0
D1
D1
0
0
D0
D0
0
0
Rev. B | Page 23 of 72
SCLK
SDIO
SCLK
SCLK
SDIO
SDO
SDIO
SDO
CS
CS
CS
A0
Figure 42. Serial Register Interface Timing LSB First
Figure 43. Timing Diagram for SPI Register Write
Figure 44. Timing Diagram for SPI Register Read
INSTRUCTION CYCLE
t
A1 A2
INSTRUCTION BIT 7
t
DCSB
DS
DATA BIT n
A3 A4
t
PWH
t
t
DH
DV
t
A5 A6 R/W D0
SCLK
t
PWL
INSTRUCTION BIT 6
DATA BIT n – 1
D0
0
0
DATA TRANSFER CYCLE
D1
D1
0
0
D2
D2
0
0
D4
D4
N
N
D5
D5
AD9148
N
N
D6
D6
N
N
D7
D7
N
N