AD5781 Analog Devices, AD5781 Datasheet - Page 20

• Manufacturer Part Number: AD5781
• Manufacturer: Analog Devices

Specifications of AD5781

• Resolution (bits): 18bit
• Dac Update Rate: 1MSPS
• Dac Settling Time: 1µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Unbuffered Vout
• Dac Input Format: Ser,SPI

AD5781
THEORY OF OPERATION
The
serial input, voltage output DAC. It operates from a V
voltage of 7.5 V to 16.5 V and a V
Data is written to the
serial interface. The
circuit that ensures the DAC output powers up to 0 V with the
V
DAC ARCHITECTURE
The architecture of the
sections. A simplified circuit diagram is shown in Figure 50.
The six MSBs of the 18-bit data-word are decoded to drive 63
switches, E0 to E62. Each of these switches connects one of 63
matched resistors to either the V
remaining 12 bits of the data-word drive the S0 to S11 switches
of a 12-bit voltage mode R-R ladder network.
Table 7. Input Shift Register Format
MSB
DB23
R/W
Table 8. Decoding the Input Shift Register
R/W
X
0
0
0
0
1
1
1
1
X is don’t care.
1
OUT
AD5781
pin clamped to AGND through a ~6 kΩ internal resistor.
Register Address
0
0
0
0
1
0
0
0
is a high accuracy, fast settling, single, 18-bit,
AD5781
AD5781
AD5781
0
0
1
1
0
0
1
1
incorporates a power-on reset
in a 24-bit word format via a 3-wire
DB22
consists of two matched DAC
REFP
SS
supply of −16.5 V to −2.5 V.
or V
0
1
0
1
0
1
0
1
REFN
voltage. The
Description
No operation (NOP). Used in readback operations.
Write to the DAC register.
Write to the control register.
Write to the clearcode register.
Write to the software control register.
Read from the DAC register.
Read from the control register.
Read from the clearcode register.
Register address
DD
DB21
supply
Rev. C | Page 20 of 28
V
The
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs (see
timing diagram).
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK, which can operate at up to 35 MHz. The
input register consists of a R/ W bit, three address bits, and
twenty data bits as shown in
this operation is shown in
V
V
V
REFNS
REFPF
REFPS
REFNF
AD5781
DB20
2R
Figure 50. DAC Ladder Structure Serial Interface
has a 3-wire serial interface ( SYNC , SCLK, and
2R
S0
12-BIT R-R LADDER
R
2R
S1
R
DB19
.....................
.....................
Figure 2
Table 7
2R
S11
.
R
. The timing diagram for
SIX MSBs DECODED INTO
Register data
63 EQUAL SEGMENTS
2R
E62
Figure 2
Data Sheet
E61
2R
..........
..........
2R
for a
E0
V
OUT
DB0
LSB