AD5735 Analog Devices, AD5735 Datasheet - Page 29

• Manufacturer Part Number: AD5735
• Description: Quad Channel, 12-Bit, Serial Input, 4-20 mA & Voltage Output DAC with Dynamic Power Control
• Manufacturer: Analog Devices

Specifications of AD5735

• Resolution (bits): 12bit
• Dac Settling Time: 11µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: I or V Out
• Dac Input Format: SPI

POWER-ON STATE OF THE AD5735
On initial power-up of the AD5735, the state of the power-on
reset circuit is dependent on the power-on condition (POC) pin.
•
•
The output ranges are not enabled, but the default output range
is 0 V to 5 V, and the clear code register is loaded with all 0s.
Therefore, if the user clears the part after power-up, the output
is actively driven to 0 V if the channel has been enabled for clear.
After device power on, or a device reset, it is recommended to
wait 100 μs or more before writing to the device to allow time
for internal calibrations to take place.
SERIAL INTERFACE
The
that operates at clock rates of up to 30 MHz and is compatible
with SPI, QSPI, MICROWIRE, and DSP standards. Data coding
is always straight binary.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of the serial
clock input, SCLK. Data is clocked in on the falling edge of SCLK.
If packet error checking (PEC) is enabled, an additional eight
bits must be written to the AD5735, creating a 32-bit serial
interface (see the Packet Error Checking section).
The DAC outputs can be updated in one of two ways: individual
DAC updating or simultaneous updating of all DACs.
Individual DAC Updating
To update an individual DAC, LDAC is held low while data is
clocked into the DAC data register. The addressed DAC output
is updated on the rising edge of SYNC . See
for timing information.
Data Sheet
AD5735
If POC = 0, both the voltage output and current output
channels power up in tristate mode.
If POC = 1, the voltage output channel powers up with
a 30 kΩ pull-down resistor to ground, and the current
output channel powers up in tristate mode.
is controlled by a versatile 3-wire serial interface
Table 3
and
Figure 3
Rev. A | Page 29 of 48
Simultaneous Updating of All DACs
To update all DACs simultaneously, LDAC is held high while
data is clocked into the DAC data register. After LDAC is taken
high, only the first write to the DAC data register of each channel
is valid; subsequent writes to the DAC data register are ignored,
although these subsequent writes are returned if a readback is
initiated. All DAC outputs are updated by taking LDAC low
after SYNC is taken high.
TRANSFER FUNCTION
Table 7 shows the input code to ideal output voltage relationship
for the
output range.
Table 7. Input Code to Ideal Output Voltage Relationship
1111
1111
1000
0000
0000
1
X = don’t care.
Straight Binary Data Coding
Figure 72. Simplified Serial Interface of the Input Loading Circuitry
MSB
V
AD5735
REFIN
LDAC
SYNC
1111
1111
0000
0000
0000
SCLK
SDIN
Digital Input
for straight binary data coding of the ±10 V
1111
1110
0000
0001
0000
DAC INPUT
INTERFACE
REGISTER
DAC DATA
REGISTER
REGISTER
for One DAC Channel
12-BIT
LSB
DAC
LOGIC
DAC
XXXX
XXXX
XXXX
XXXX
XXXX
1
AMPLIFIERS
CALIBRATION
OUTPUT
AND GAIN
Analog Output
V
+2 V
+2 V
0 V
−2 V
−2 V
OFFSET
OUT
SDO
REF
REF
REF
REF
× (2047/2048)
× (2046/2048)
× (2047/2048)
V
OUT_x
AD5735