CS8406-CZZ Cirrus Logic Inc, CS8406-CZZ Datasheet - Page 31

• Manufacturer Part Number: CS8406-CZZ
• Description: IC XMITTER DGTL 192KHZ 28TSSOP
• Manufacturer: Cirrus Logic Inc
• Type: Digital Audio Interface Transmitterr

Specifications of CS8406-CZZ

• Package / Case: 28-TSSOP
• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Operating Supply Voltage: 3.3 V / 5.0 V
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1017 - BOARD EVAL FOR CS8416 RCVR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1121-5

DS580F5
VD
VL
GND
RST
H/S
TXN
TXP
OMCK
ISCLK
ILRCK
SDIN
SFMT0
SFMT1
APMS
HWCK0
HWCK1
TCBLD
TCBL
CEN
V
U
COPY/C
EMPH
AUDIO
ORIG
23
22
24
25
26
21
13
12
14
10
20
27
15
16
17
18
19
28
11
6
9
4
5
1
3
Digital Power (Input) - Digital core power supply. Typically +3.3 V or +5.0 V.
Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
Ground (Input) - Ground for I/O and core logic.
Reset (Input) - When RST is low, the CS8406 enters a low power mode and all internal states are reset.
On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable
in frequency and phase. This is particularly true in Hardware Mode with multiple CS8406 devices, where
synchronization between devices is important.
Hardware/Software Control Mode Select (Input) - Determines the method of controlling the operation
of the CS8406, and the method of accessing CS and U data. Hardware Mode provides an alternate
mode of operation, and access to CS and U data is provided by dedicated pins. To select Hardware
Mode, this pin should be permanently tied to VL.
Differential Line Drivers (Output) - These pins transmit biphase encoded data. The drivers are pulled
low while the CS8406 is in the reset state.
Master Clock (Input) - The frequency can be set through the HWCK[1:0] pins.
Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin.
Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN
pin.
Serial Audio Data Port (Input) - Audio data serial input pin.
Serial Audio Data Format Select (Input) - Selects the serial audio input port format. See
page
Serial Audio Data Port Master/Slave Select (Input) - APMS should be connected to VL to set serial
audio input port as a master or connected to GND to set the port as a slave.
OMCK Clock Ratio Select (Input) - Selects the ratio of OMCK to the input sample rate (Fs). A pull-up to
VL or pull-down to GND is required to set the appropriate mode. See
Transmit Channel Status Block Direction (Input) - Connect TCBLD to VL to set TCBL as an output.
Connect TCBLD to GND to set TCBL as an input.
Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during
the first sub-frame of a transmitted channel status block, and low at all other times. When operated as
input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be
the start of a channel status block.
C Bit Enable (Input) - Determines how the channel status data bits are input. When CEN is low, Hard-
ware Mode A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected
channel status data. When CEN is high, Hardware Mode B is selected, where the COPY/C pin is used
to enter serial channel status data.
Validity Bit (Input) - In Hardware Modes A and B, the V pin input determines the state of the validity bit
in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.
User Data Bit (Input) - In Hardware Modes A and B, the U pin input determines the state of the user
data bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK.
COPY Channel Status Bit/C Bit (Input) - In Hardware Mode A (CEN = 0), the COPY/C and ORIG pins
determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream,
see
which is sampled on both edges of LRCK.
Pre-Emphasis Indicator (Input) - In Hardware Mode A (CEN = 0), the EMPH pin low sets the 3 empha-
sis channel status bits to indicate 50/15 μs pre-emphasis of the transmitted audio data. If EMPH is high,
then the three EMPH channel status bits are set to 000, indicating no pre-emphasis.
Audio Channel Status Bit (Input) - In Hardware Mode A (CEN = 0), the AUDIO pin determines the
state of the audio/non audio Channel Status bit in the outgoing AES3 data stream.
ORIG Channel Status Bit Control (Input) - In Hardware Mode A (CEN = 0), the ORIG and COPY/C
pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data
stream, see
Table 2 on page
29.
Table 2 on page
29. In Hardware Mode B, the COPY/C pin becomes the direct C bit input data pin,
29.
Table 4 on page
29.
CS8406
Table 3 on
31