AD7701 Analog Devices, AD7701 Datasheet - Page 11

• Manufacturer Part Number: AD7701
• Description: 16-Bit Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD7701

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 16kSPS
• Interface: Ser
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip 2.5V,Uni 2.5V
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC,SOP

INPUT SIGNAL CONDITIONING
Reference voltages from 1 V to 3 V may be used with the AD7701
with little degradation in performance. Input ranges that cannot
be accommodated by this range of reference voltages may be
achieved by input signal conditioning. This may take the form
of gain to accommodate a smaller signal range, or passive attenua-
tion to reduce a larger input voltage range.
Source Resistance
If passive attenuators are used in front of the AD7701, care must
be taken to ensure that the source impedance is sufficiently low.
The AD7701 has an analog input with over 1 GΩ dc input
resistance. In parallel with this, there is a small dynamic load that
varies with the clock frequency (see Figure 13). Each time the
analog input is sampled, a 10 pF capacitor draws a charge packet
of maximum 1 pC (10 pF × 100 mV) from the analog source
with a frequency f
yields an average current draw of 16 nA. After each sample, the
AD7701 allows 62 clock periods for the input voltage to settle.
The equation that defines settling time is:
where
V
V
R is the value of the input source resistance.
C is the 10 pF sample capacitor.
t is equal to 62/f
From this, the following equation can be developed, which
gives the maximum allowable source resistance, R
an error of V
Provided the source resistance is less than this value, the analog
input will settle within the desired error band in the requisite 62
clock periods. Insufficient settling leads to offset errors. These
can be calibrated in system calibration schemes.
If a limit of 10 µV (0.25 LSB at 16 bits) is set for the maximum
offset voltage, then the maximum allowable source resistance is
160 kΩ from the above equation, assuming that there is no
external stray capacitance.
REV. E
O
IN
Figure 13. Equivalent Input Circuit and Input Attenuator
is the final settled value.
is the value of the input signal.
R
S (MAX )
R1
E
R2
:
CLKIN
=
CLKIN
f
AGND
CLKIN
.
V
O
C
/256. For a 4.096 MHz CLKIN, this
EXT
=
V
×(10 pF ) × l n (100mV /V
IN
A
[
IN
1
V
OS
−
e
62
100mV
−
t RC
]
AD7701
10pF
C
IN
S(MAX)
E
)
, for
–11–
An RC filter may be added in front of the AD7701 to reduce
high frequency noise. With an external capacitor added from
A
allowable source resistance:
The practical limit to the maximum value of source resistance is
thermal (Johnson) noise. A practical resistor may be modeled as
an ideal (noiseless) resistor in series with a noise voltage source
or in parallel with a noise current source:
where
k is Boltzmann’s constant (1.38 × 10
T is temperature in degrees Kelvin (°C + 273).
Active signal conditioning circuits such as op amps generally do
not suffer from problems of high source impedance. Their open-
loop output resistance is normally only tens of ohms and, in any
case, most modern general-purpose op amps have sufficiently
fast closed-loop settling time for this not to be a problem. Offset
voltage in op amps can be eliminated in a system calibration
routine. With the wide dynamic range and small LSB size of the
AD7701, noise can also be a problem, but the digital filter will
reject most broadband noise above its cutoff frequency. How-
ever, in certain applications there may be a need for analog
input filtering.
Antialias Considerations
The digital filter of the AD7701 does not provide any rejection
at integer multiples of the sampling frequency (nf
where n = 1, 2, 3 . . . ).
With a 4.096 MHz master clock, there are narrow (± 10 Hz)
bands at 16 kHz, 32 kHz, 48 kHz, and so on, where noise
passes unattenuated to the output.
However, due to the AD7701’s high oversampling ratio of 800
(16 kHz to 20 Hz), these bands occupy only a small fraction of
the spectrum and most broadband noise is filtered. The reduc-
tion in broadband noise is given by:
where
e
f
f
Since the ratio of f
broadband white noise by 96.5% independent of the master
clock frequency.
S
C
lN
R
IN
is the filter –3 dB corner frequency (f
is the sampling frequency (f
S (Max)
and e
to AGND, the following equation will specify the maximum
OUT
=
f
are rms noise terms referred to the input.
CLKIN
e
OUT
S
× (
i
to f
n
C
= e
= 4
V
IN
CLKIN
n
IN
= 4
+
kTRf R Amperes
C
2 f
EXT
is fixed, the digital filter reduces
CLKIN
kTRf Volts
C
/ f
) × ln
/256).
S
62
–23



= 0.035 e
100 mV × C
CLKIN
J/K).
/409600).
IN
AD7701
IN
V
E
/ (C
CLKlN
IN
+ C
/256,
EXT
)


