AD676 Analog Devices, AD676 Datasheet
AD676
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AD676 Summary of contents
Page 1
... An analog ground sense is provided for the analog input. Separate analog and digital grounds are also provided. The AD676 is available in a 28-pin plastic DIP or 28-pin side- brazed ceramic package. A serial-output version, the AD677, is available in a 16-pin 300 mil wide ceramic or plastic package. ...
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... 1.0 kHz –0.05 dB, Bandwidth = fs/2 unless otherwise indicated. All measurements referred –2– 10%) DD AD676K/B Max Min Typ Max –88 –97 –90 0.004 0.0014 0.003 –97 0.0014 –92 0.0025 –98 –102 – ...
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... V V REF REF * 2 50* 50* 6 100 14 14 480 360 480 AD676 Units C C Bits LSB LSB LSB Bits % FSR % FSR % FSR % FSR % FSR % FSR % FSR % FSR % FSR LSB LSB LSB ...
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... AD676 TIMING SPECIFICATIONS (T Parameter 2 Conversion Time 3 CLK Period Calibration Time Sampling Time (Included CAL to BUSY Delay BUSY to SAMPLE Delay SAMPLE to BUSY Delay 4 CLK HIGH 4 CLK LOW SAMPLE LOW to 1st CLK Delay SAMPLE LOW Output Delay Status Delay CAL HIGH Time ...
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... AD676JD +70 C AD676KD +70 C AD676AD – +85 C AD676BD – +85 C NOTES 1 For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the AD676/883 data sheet Ceramic DIP. ABSOLUTE MAXIMUM RATINGS AGND . . . . . . . . . . . . . . . . . . . . . . . . –0 +18 V ...
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... Control” paragraph). During calibration, SAMPLE should be held LOW. If HIGH dur- ing calibration, diagnostic information will appear on the two LSBs (Pins 5 and 6). Master Clock Input. The AD676 requires 17 clock cycles to execute a conversion. Digital Ground. +12 V Analog Supply Voltage. ...
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... The IMD products are normalized input signal. APERTURE DELAY Aperture delay is the time required after SAMPLE pin is taken LOW for the internal sample-hold of the AD676 to open, thus holding the value ...
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... The accu- mulated values in RAM are then used during subsequent con- versions to adjust conversion results accordingly. As shown in Figure 1, when CAL is taken HIGH the AD676 in- ternal circuitry is reset, the BUSY pin is driven HIGH, and the ADC prepares for calibration. This is an asynchronous hard- ware reset and will interrupt any conversion or calibration cur- rently in progress ...
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... AD676 SAMPLE command from the system clock when a continuous convert mode is desirable. Pin 9 (2QC) pro- vides a 96 kHz sample rate for the AD676 when used with a 12.288 MHz system clock. Alternately, Pin 8 (2QD) could be used for a 48 kHz rate. ...
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... For bypassing to be effective, certain guidelines should be followed. Decoupling capacitors, typically 0.1 F, should be placed as closely as possible to each power supply pin of the AD676 essential that these capacitors be placed physically close to the IC to minimize the inductance of the PCB trace between the capacitor and the supply pin. The ...
Page 11
... The input voltage range is determined by the value of the refer- ence voltage; in general, a reference voltage of n volts allows an input range of n volts. The AD676 is specified for both 10 V and 5.0 V references reference will typically require support circuitry operated from 15 V supplies; a 5.0 V refer- ence may be used with 12 V supplies ...
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... AD676 AD586 output, thereby optimizing the overall performance of the AD676 recommended that high qual- ity tantalum capacitor be tied between the V AD676 and ground to minimize the impedance on the reference. AD587 10µF 0.1µF GND 10 +15V 78L12 100µF 0.01µ ...
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... AC PERFORMANCE AC parameters, which include S/(N+D), THD, etc., reflect the AD676’s effect on the spectral content of the analog input sig- nal. Figures 12 through 16 provide information on the AD676’s ac performance under a variety of conditions general rule, averaging the results from several conversions reduces the effects of noise, and therefore improves such param- eters as S/(N+D) ...
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... The 80286 16-bit microprocessor can be interfaced to a buff- ered AD676 without any generation of wait states. As seen in Figure 11, BUSY can be used both to control the AD676 clock and to alert the processor when new data is ready. In the system shown, the 80286 should be configured in an edge triggered, di- rect interrupt mode (integrated controller provides the interrupt vector) ...
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... Figure 15. IMD Plot for f IN 1055 Hz (fb kSPS + +12V 100 1k 10k 100k RIPPLE FREQUENCY – kSPS 0.13 V p-p RIPPLE –15– AD676 THD S/(N+D) –50 –40 –30 –20 –10 INPUT AMPLITUDE – 1008 Hz (fa), IN –12V 1M = 1.06 kHz) 0 ...
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... AD676 0.005 (0.13) MIN 28 1 0.225 (5.72) MAX 0.026 (0.66) 0.200 (5.08) 0.125 (3.18) 0.014 (0.36) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Pin Ceramic DIP Package (D-28) 0.100 (2.54) MAX 15 14 1.490 (37.85) MAX 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) 0.070 (1.78) 0.100 (2.54) 0.030 (0.76) BSC –16– 0.610 (15.49) 0.500 (12.70) 0.018 (0.46) 0.008 (0.20) MIN 0.620 (15.75) 0.590 (14.99) ...