AD677 Analog Devices, AD677 Datasheet - Page 6

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AD677

Manufacturer Part Number
AD677
Description
16-Bit, Serial, 100 kSPS Sampling ADC.
Manufacturer
Analog Devices
Datasheet

Specifications of AD677

Resolution (bits)
16bit
# Chan
1
Sample Rate
100kSPS
Interface
Ser
Analog Input Type
SE-Bip
Ain Range
Bip (Vref)
Adc Architecture
SAR
Pkg Type
DIP,SOIC

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AD677
DIP Pin SOIC Pin
.9
10
11
12
13
14
15
16
6, 7
Type: AI = Analog Input
1
2
3
4
5
8
DI = Digital Input
DO = Digital Output
P = Power
1
2
3
8
12
15
16
17
21
22, 23
26
27
28
4, 5, 9, 10, 11,
13, 14, 18, 19,
20, 24, 25
6, 7
SAMPLE
SDATA
DGND
AGND
CLK
V
NC
NC
CC
1
2
4
5
3
7
8
6
NC = NO CONNECT
DIP Pinout
(Not to Scale)
TOP VIEW
Type
SAMPLE
CLK
SDATA
DGND
V
AGND
AGND SENSE
V
V
V
V
SCLK
BUSY
CAL
NC
AD677
CC
IN
REF
EE
DD
12
16
15
10
14
13
11
9
CAL
BUSY
V
V
SCLK
V
V
AGND
SENSE
IN
EE
DD
REF
Name
DI
DI
DO
P
P
P
AI
AI
P
P
DO
DO
DI
_
AI
PIN DESCRIPTION
Master Clock Input. The AD677 requires 17 clock pulses to execute a
Serial Output Data Controlled by SCLK.
Digital Ground.
Analog Ground.
Analog Input Voltage.
External Voltage Reference Input.
Clock Output for Data Read, derived from CLK.
Status Line for Converter. Active HIGH, indicating a conversion or
Calibration Control Pin.
No Connection. No connections should be made to these pins.
Description
V
controls the suite of the internal sample-hold amplifier and the falling edge
initiates conversion. During calibration, SAMPLE should be held LOW. If
HIGH during calibration, diagnostic information will appear on SDATA.
conversion. CLK is also used to derive SCLK.
+12 V Analog Supply Voltage.
Analog Ground Sense.
–12 V Analog Supply Voltage.
+5 V Logic Supply Voltage.
calibration in progress.
IN
Acquisition Control Pin. Active HIGH. During conversion, SAMPLE
–6–
SAMPLE
SDATA
DGND1
DGND2
AGND
CLK
V
NC
NC
NC
NC
NC
NC
NC
CC
10
11
12
13
14
1
4
9
2
3
5
7
8
6
SOIC Pinout
NC = NO CONNECT
(Not to Scale)
TOP VIEW
AD677
27
26
25
24
21
20
18
16
28
23
22
19
17
15
NC
CAL
BUSY
SCLK
NC
NC
V
V
V
NC
NC
V
V
AGND
SENSE
REF
DD1
DD2
EE
IN
REV. A

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