AD7892 Analog Devices, AD7892 Datasheet - Page 12

• Manufacturer Part Number: AD7892
• Description: True Bipolar Input, Single Supply, Parallel, 12-Bit 600 kSPS ADC
• Manufacturer: Analog Devices

Specifications of AD7892

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 600kSPS
• Interface: Par,Ser
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip 10V,Bip 2.5V,Bip 5.0V,Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC

AD7892
MICROPROCESSOR INTERFACING
The AD7892 features both high speed parallel and serial inter-
faces, allowing considerable flexibility in interfacing to micro-
processor systems. To obtain optimum performance from the
part, data should not be read during conversion and this limits
the achievable throughput rate in serial mode to 400 kSPS for
the AD7892-3.
Figures 6, 7 and 9 show some typical interface circuits between
the AD7892 and popular DSP processors. Figure 8 shows an
interface between the part and a gate array or ASIC where data
is clocked into the ASIC by the AD7892 itself at the end of
conversion. In all cases, the CONVST signal is generated from
an external timer to ensure equidistant sampling.
AD7892 to ADSP-2101 Interface
Figure 6 shows a parallel interface between the AD7892 and the
ADSP-2101 DSP processor. CONVST starts conversion and at
the end of conversion the falling edge of the EOC output pro-
vides an interrupt request to the ADSP-2101.
AD7892 to TMS320C25 Interface
Figure 7 shows a parallel interface between the AD7892 and the
TMS320C25 DSP processor. CONVST starts conversion and
at the end of conversion the falling edge of the EOC output
provides an interrupt request to the TMS320C25.
ADSP-2101
TMS320C25
DMA13–DMA0
DMD15–DMD0
A15–A0
READY
D15–D0
STRB
IRQn
DMS
MSC
R/W
RD
INT
IS
ADDRESS BUS
EN
ADDRESS BUS
ADDRESS DECODE
ADDRESS DECODE
EN
G2
DATA BUS
LOGIC
DATA BUS
LOGIC
TIMER
TIMER
DB11–DB0
CONVST
CS
EOC
RD
AD7892
DB11–DB0
CS
CONVST
RD
EOC
AD7892
EOC Pulse Provides CS and RD
Figure 8 shows a parallel interface between the AD7892 and a
gate array or ASIC. CONVST starts conversion and at the end
of conversion the falling edge of the EOC output provides the
CS and RD pulse to latch data out of the AD7892 and into the
gate array/ASIC. This scheme allows for the fastest possible
throughput rate with the part as no time is lost in interrupt
service routines and as soon as data is available from the part it
is transferred out of it.
AD7892 to DSP56000 Interface
Figure 9 shows a serial interface between the AD7892 and the
DSP56000 DSP processor. CONVST starts conversion and at
the end of conversion the falling edge of the EOC output pro-
vides an interrupt request to the DSP56000.
ARRAY/ASIC
DSP56000
GATE
DB11–DB0
ENABLE
IRQA
SCK
SRD
SC1
DATA BUS
TIMER
TIMER
SDATA
CONVST
EOC
SCLK
RFS
AD7892
EOC
CS
DB11–DB0
CONVST
RD
AD7892