AD9059 Analog Devices, AD9059 Datasheet

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AD9059

Manufacturer Part Number
AD9059
Description
Dual 8-Bit, 60 MSPS A/D Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9059

Resolution (bits)
8bit
# Chan
2
Sample Rate
60MSPS
Interface
Par
Analog Input Type
SE-Uni
Ain Range
1 V p-p
Adc Architecture
Pipelined
Pkg Type
SOP

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PRODUCT DESCRIPTION
The AD9059 is a dual 8-bit monolithic analog-to-digital converter
optimized for low cost, low power, small size, and ease of use.
With a 60 MSPS encode rate capability and full-power analog
bandwidth of 120 MHz typical, the component is ideal for
applications requiring multiple ADCs with excellent dynamic
performance.
To minimize system cost and power dissipation, the AD9059
includes an internal 2.5 V reference and dual track-and-hold
circuits. The ADC requires only a 5 V power supply and an
encode clock. No external reference or driver components are
required for many applications.
The AD9059’s single encode input is TTL/CMOS compatible
and simultaneously controls both internal ADC channels. The
parallel 8-bit digital outputs can be operated from 5 V or 3 V
supplies. A power-down function may be exercised to bring
total consumption to <12 mW when ADC data is not required
for lengthy periods of time. In power-down mode, the digital
outputs are driven to a high impedance state.
Fabricated on an advanced BiCMOS process, the AD9059
is available in a space-saving 28-lead shrink small outline
package (28-lead SSOP) and is specified over the industrial
temperature range (–40°C to +85°C).
Customers desiring single-channel digitization may consider the
AD9057, a single 8-bit, 60 MSPS monolithic based on the
AD9059 ADC core. The AD9057 is available in a 20-lead shrink
small outline package (20-lead SSOP) and is specified over the
industrial temperature range.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
FEATURES
Dual 8-Bit ADCs on a Single Chip
Low Power: 400 mW Typical
On-Chip 2.5 V Reference and Track-and-Hold
1 V p-p Analog Input Range
Single 5 V Supply Operation
5 V or 3 V Logic Interface
120 MHz Analog Bandwidth
Power-Down Mode: <12 mW
APPLICATIONS
Digital Communications (QAM Demodulators)
RGB and YC/Composite Video Processing
Digital Data Storage Read Channels
Medical Imaging
Digital Instrumentation
Dual 8-Bit, 60 MSPS A/D Converter
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
VREF
AINA
AINB
FUNCTIONAL BLOCK DIAGRAM
D7A (MSB)
D0A (LSB)
V
PWRDN
T/H
PIN CONFIGURATION
T/H
D
VREF
© 2003 Analog Devices, Inc. All rights reserved.
AINA
GND
D6A
D5A
D4A
D3A
D2A
D1A
V
V
DD
AD9059
D
2.5V
10
11
12
13
14
PWRDN
1
2
3
4
5
6
7
8
9
GND
(Not to Scale)
TOP VIEW
AD9059
ADC
ADC
V
B
A
DD
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D7B (MSB)
AINB
GND
ENCODE
V
GND
V
D0B (LSB)
D6B
D5B
D4B
D3B
D2B
D1B
D
DD
8
8
ENCODE
AD9059
D7A–D0A
D7B–D0B
www.analog.com

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AD9059 Summary of contents

Page 1

... Customers desiring single-channel digitization may consider the AD9057, a single 8-bit, 60 MSPS monolithic based on the AD9059 ADC core. The AD9057 is available in a 20-lead shrink small outline package (20-lead SSOP) and is specified over the industrial temperature range. ...

Page 2

... I 25°C V 25°C I 25°C V 25°C I 25°C V 25°C I 25°C V 25°C V 25°C V 25°C V 25°C V –2– AD9059BRS Min Typ Max Unit 8 Bits 0.75 2.0 LSB 2.5 LSB 0.75 2.0 LSB 2.5 LSB Guaranteed –6 –2 – ± ...

Page 3

... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9059 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

Page 4

... EH t PULSEWIDTH LOW EL t OUTPUT VALID TIME V t OUTPUT PROP DELAY PD Figure 1. Timing Diagram PIN CONFIGURATION 1 AINA 2 VREF PWRDN GND AD9059 TOP VIEW (Not to Scale) D7A (MSB D6A D5A 9 D4A 10 D3A 11 D2A 12 D1A 13 D0A (LSB Pin No. ...

Page 5

... ENCODE = 60MSPS AIN = –0.5dBFS 100 ANALOG INPUT FREQUENCY (MHz) TPC 3. SINAD/SNR vs. AIN Frequency REV. A Typical Performance Characteristics–AD9059 –30 –35 –40 –45 –50 –55 –60 –65 – TPC 4. Harmonic Distortion vs. AIN Frequency 0 –10 –20 –30 – ...

Page 6

... AD9059 600 AIN = 10.3MHz, –0.5dBFS 550 500 450 400 350 300 250 ENCODE RATE (MSPS) TPC 7. Power Dissipation vs. Encode Rate 45.5 SNR 45.0 44.5 SINAD 44.0 43.5 43.0 ENCODE = 60MSPS 42.5 AIN = 10.3MHz, –0.5dBFS 42.0 41.5 – TEMPERATURE ( TPC 8. SINAD/SNR vs. Temperature 0 –0.2 – ...

Page 7

... Figure 3. DC-Coupled AD9059 (VIN Inverted) Voltage Reference A stable and accurate 2.5 V voltage reference is built into the AD9059 (VREF). The reference output is used to set the ADC gain/offset and can provide dc bias for the analog input signals. The internal reference is tied to the ADC circuitry through an 800 Ω ...

Page 8

... PWRDN pin; they cannot be shut down or turned on independently. Applications The wide analog bandwidth of the AD9059 makes it attractive for a variety of high performance receiver and encoder applications. Figure 4 shows the dual ADC in a typical low cost I and Q demodulator implementation for cable, satellite, or wireless LAN modem receivers ...

Page 9

... V typical) to center the voltage for proper ADC input drive. For dc-coupled operation, connect (analog input A to R11), E14 to E13 (amplifier output to analog input A of AD9059 (analog input B to R10), and E11 to E10 (amplifier output to analog input B of AD9059) using the board jumper connectors. ...

Page 10

... R12 – J11 0.1µ 0.1µF 0.1µF 0.1µF DECOUPLING CAPS J12, GND Figure 7. AD9059 Dual Evaluation Board Schematic J9, V C12 0.1µF C16 10µ AD9059RS E14 E13 1 AINA E15 2 VREF 3 R15 PWRDN ...

Page 11

... REV. A Figure 8. Evaluation Board Layout (Top) Figure 9. Evaluation Board Layout (Bottom) –11– AD9059 ...

Page 12

... AD9059 2.00 MAX 0.05 MIN Revision History Location 4/03—Data Sheet changed from REV REV. A. Renumbered Figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9. 5.60 8.20 5.30 7.80 5.00 7. 1.85 1.75 0.10 1.65 COPLANARITY 0.25 0.09 0.38 0.65 BSC 0.22 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-150AH – ...

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