AD7813 Analog Devices, AD7813 Datasheet - Page 9

• Manufacturer Part Number: AD7813
• Description: +2.7 V to +5.5 V, 400 kSPS 8-/10-Bit Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7813

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 400kSPS
• Interface: Byte
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

PARALLEL INTERFACE
The parallel interface of the AD7813 is eight bits wide. The
output data buffers are activated when both CS and RD are
logic low. At this point the contents of the data register are
placed on the 8-bit data bus. Figure 15 shows the timing dia-
gram for the parallel port. As previously explained, two succes-
sive read operations must take place in order to access the 10-bit
conversion result. The first read places the 8 MSBs on the data
bus and the second read places the 2 LSBs on the data bus. The
2 LSBs appear on DB7 and DB6, with DB5–DB0 set to logic zero.
REV. C
EXT CONVST
EXT CONVST
INT CONVST
INT CONVST
DB7–DB0
CONVST
DB7–DB0
DB7–DB0
BUSY
CS/RD
CS/RD
BUSY
BUSY
RD
CS
t
POWER-UP
t
3
t
POWER-UP
t
t
2
1
t
t
t
2
3
3
t
4
t
6
t
Figure 15. Parallel Port Timing
t
1
1
Figure 13. Mode 1 Operation
Figure 14. Mode 2 Operation
8 MSBs
–9–
8 MSBs
8 MSBs
Further read operations will access the 8 MSBs and 2 LSBs of
the 10-bit ADC conversion result again. The parallel interface
of the AD7813 is reset when BUSY goes logic high. This feature
allows the AD7813 to be used as an 8-bit converter if the user
only wishes to access the 8 MSBs of the conversion. Care must
be taken to ensure that a read operation does not occur while
BUSY is high. Data read from the AD7813 while BUSY is high
will be invalid. For optimum performance the read operation
should end at least 100 ns (t
next CONVST.
t
7
t
5
t
8
2 MSBs
2 LSBs
10
) prior to the falling edge of the
t
9
AD7813