AD7827 Analog Devices, AD7827 Datasheet - Page 6

• Manufacturer Part Number: AD7827
• Description: 3/5V, 1 MSPS, 8-Bit, Serial Interface Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7827

• Resolution (bits): 8bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser
• Analog Input Type: SE-Uni
• Ain Range: Uni 2.0V,Uni 2.5V
• Adc Architecture: Pipelined
• Pkg Type: DIP,SOIC

AD7827
CIRCUIT DESCRIPTION
The AD7827 consists of a track-and-hold amplifier followed by
a half-flash analog-to-digital converter. This device uses a half-
flash conversion technique where one 4-bit flash ADC is used to
achieve an 8-bit result. The 4-bit flash ADC contains a sampling
capacitor followed by 15 comparators that compare the unknown
input to a reference ladder to get a 4-bit result. This first flash,
i.e., coarse conversion, provides the 4 MSBs. For a full 8-bit
reading to be realized, a second flash, i.e., a fine conversion,
must be performed to provide the 4 LSBs. The 8-bit word is
then placed in the serial shift register.
Figures 2 and 3 below show simplified schematics of the ADC.
When the ADC starts a conversion, the track-and-hold goes into
hold mode and holds the analog input for 120 ns. This is the
acquisition phase as shown in Figure 2 when Switch 2 is in
Position A. At the point when the track-and-hold returns to its
track mode, this signal is sampled by the sampling capacitor as
Switch 2 moves into Position B. The first flash occurs at this
instant and is then followed by the second flash. Typically the
first flash is complete after 100 ns, i.e., at 220 ns, while the end
V
V
IN
IN
REFERENCE
REFERENCE
T/H
T/H
HOLD
HOLD
A
SW2
A
TIMING AND
SW2
TIMING AND
CONTROL
CONTROL
Figure 2. ADC Acquisition Phase
Figure 3. ADC Conversion Phase
LOGIC
LOGIC
B
B
CAPACITOR
CAPACITOR
SAMPLING
SAMPLING
R16
R15
R14
R13
R16
R15
R14
R13
R1
R1
15
14
13
15
14
13
1
1
.
.
.
.
.
.
.
.
D
D
OUT
OUT
–6–
of the second flash, and hence the 8-bit conversion result, is
available at 330 ns. As shown in Figure 4 the track-and-hold
returns to track mode after 120 ns, and so starts the next acqui-
sition before the end of the current conversion. Figure 6 shows
the ADC transfer function.
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7827.
The serial interface is implemented using three wires; the RFS is
a logic output and the serial clock is continuous. The Receive
Frame Sync signal (RFS) idles high, the falling edge of CONVST
initiates a conversion and the first rising edge of the serial clock
after the end of conversion causes the RFS signal to go low.
This falling edge of RFS is used to drive the RFS on a micro-
processor—see Serial Interface section for more details. V
connected to a voltage source such as the AD780, while V
connected to a voltage source of 3 V
to the proximity of the CONVST and V
mended to use a 10 nF decoupling capacitor on V
is first connected the AD7827 powers up in a low current mode,
i.e., power-down. A rising edge on the CONVST pin will cause
the AD7827 to fully power up. For applications where power
consumption is of concern, the automatic power-down at the
end of a conversion should be used to improve power perfor-
mance. See the Power-Down Options section of this data sheet.
CONVST
+3V
SCLK
D
TRACK
RFS
+5V
OUT
0V TO 2.5V (V
SUPPLY
10% OR
0V TO 2V (V
10%
t
120ns
HOLD
1
Figure 5. Typical Connection Diagram
t
2
10 F
Figure 4. Track-and-Hold Timing
DD
DD
INPUT
= 5V)
= 3V)
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0.1 F
t
3
2
3
V
GND
V
IN
DD
t
4
AD7827
7
TRACK
AD780
V
2.5V
t
REF
8
5
CONVST
10% or 5 V
IN
SCLK
D
SERIAL INTERFACE
RFS
OUT
6
pins, it is recom-
THREE-WIRE
7
IN
t
8
4
. When V
10%. Due
REV. 0
REF
DD
C/ P
HOLD
t
is
is
DD
10