AD7856 Analog Devices, AD7856 Datasheet - Page 24

• Manufacturer Part Number: AD7856
• Description: 5 V Single-Supply, 8-Channel, 14-Bit, 285 kSPS, Serial Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7856

• Resolution (bits): 14bit
• # Chan: 8
• Sample Rate: 285kSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

AD7856
Interface
Mode
1
2
DETAILED TIMING SECTION
Mode 1 (2-Wire 8051 Interface)
The read and write takes place on the DIN line and the conver-
sion is initiated by pulsing the CONVST pin (note that in every
write cycle the 2/3 MODE bit must be set to 1). The conversion
may be started by setting the CONVST bit in the control regis-
ter to 1 instead of using the CONVST pin.
Figures 31 and 32 show the timing diagrams for Operating
Mode 1 in Table X where the AD7856 is in the 2-wire interface
mode. Here the DIN pin is used for both input and output as
shown. The SYNC input is level-triggered active low and can be
pulsed (Figure 31) or can be constantly low (Figure 32).
Table X. Interface Mode Description
Figure 31. Timing Diagram for Read/Write Operation with DIN as an Input/Output (i.e., Mode 1)
SYNC (I/P)
SCLK (I/P)
POLARITY PIN LOGIC HIGH
8XC51
8XL51
PIC17C42
68HC11
68L11
68HC16
PIC16C64
ADSP-21xx
DSP56000
DSP56001
DSP56002
DSP56L002
Figure 32. Timing Diagram for Read/Write Operation with DIN as an Input/Output and
SYNC Input Tied Low (i.e., Interface Mode 1)
DIN (I/O)
SCLK (I/P)
POLARITY PIN LOGIC HIGH
Processor/
Controller
DIN (I/O)
t
3
DB15
t
t
8
7
DB15
1
t
t
8
1
7
t
t
3
6
DATA WRITE
t
t
Comment
(2-Wire)
(DIN Is an Input/
Output Pin)
(3-Wire, SPI)
(Default Mode)
= –0.4
= 45/75ns MAX (A/K),
6
13
DATA WRITE
= 45/75ns MAX (A/K),
= 90ns MAX,
t
SCLK
MIN (NONCONTINUOUS SCLK) –/+ 0.4
DB0
t
t
13
16
DB0
14
16
t
= 50ns MIN
12
t
t
11
DIN BECOMES AN OUTPUT
7
t
= 30/40ns MIN (A/K),
7
–24–
= 30/40ns MIN (A/K),
3-STATE
In Figure 31 the part samples the input data on the rising edge
of SCLK. After the 16th rising edge of SCLK the DIN is con-
figured as an output. When the SYNC is taken high the DIN is
three-stated. Taking SYNC low disables the three-state on the
DIN pin and the first SCLK falling edge clocks out the first data
bit. Once the 16 clocks have been provided the DIN pin will
automatically revert back to an input after a time, t
a continuous SCLK shown by the dotted waveform in Figure 31
can be used provided that the SYNC is low for only 16 clock
pulses in each of the read and write cycles.
In Figure 32 the SYNC line is permanently tied low and this
results in a different timing arrangement. With SYNC perma-
nently tied low the DIN pin will never be three-stated. The 16th
rising edge of SCLK configures the DIN pin as an input or an
output as shown in the diagram. Here no more than 16 SCLK
pulses must occur for each of the read and write operations.
If reading from and writing to the calibration registers in this
interface mode, all the selected calibration registers must be
read from or written to. The read and write operations cannot
be aborted. When reading from the calibration registers, the
DIN pin will remain as an output for the full duration of all the
calibration register read operations. When writing to the calibra-
tion registers, the DIN pin will remain as an input for the full
duration of all the calibration register write operations.
NOTE: Initiating conversions in software is not recommended
in Mode 1 operation.
A degradation of 0.3 LSB in linearity can be expected when
operating in Mode 1; however, when hardware initiation of
conversions is used, all other specifications that apply to Mode 2
operation also apply to Mode 1.
t
5
t
3
t
8
1
t
= 20ns MIN
8
1
DB15
= 20ns MIN,
t
t
DB15
6
SCLK
t
6
ns MIN/MAX (CONTINUOUS SCLK),
DATA READ
DATA READ
6
t
6
DIN BECOMES AN INPUT
t
6
DIN BECOMES AN INPUT
16
16
DB0
t
DB0
11
t
14
t
14
14
. Note that
REV. A