AD7707 Analog Devices, AD7707 Datasheet - Page 25

• Manufacturer Part Number: AD7707
• Manufacturer: Analog Devices

Specifications of AD7707

• Resolution (bits): 16bit
• # Chan: 3
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Bip
• Ain Range: Bip (Vref)/(PGA Gain),Bip 10V,Bip 5.0V,Uni (Vref)/(PGA Gain),Uni 10V,Uni 5.0V
• Adc Architecture: Sigma-Delta
• Pkg Type: SOIC,SOP

ANALOG INPUT
ANALOG INPUT RANGES
The AD7707 contains two low level pseudo differential analog
input channels, AIN1 and AIN2. These input pairs provide
programmable-gain, differential input channels that can handle
either unipolar or pseudo bipolar input signals. It should be
noted that the bipolar input signals are referenced to the LOCOM
input. The AD7707 also has a high level analog input channel
AIN3, which is referenced to HICOM. Figure 13 shows the input
structure on the high level input channel.
In normal 5 V operation, VBIAS is normally connected to 2.5 V
and HICOM is connected to AGND. This arrangement ensures
that the voltages seen internally are within the common-mode
range of the buffer in buffered mode and within the supply range in
unbuffered mode. This device can be programmed to operate in
either buffered or unbuffered mode via the BUF bit in the setup
register. Note that the signals on AIN3 are with respect to the
HICOM input and not with respect to AGND or DGND.
The differential voltage seen by the AD7707 when using the
high level input channel is the difference between AIN3(+) and
AIN3(−) on the mux as shown in Figure 13.
In unbuffered mode, the common-mode range of the low level
input channels is from AGND − 100 mV to AV
means that in unbuffered mode, the part can handle both unipolar
and bipolar input ranges for all gains. Absolute voltages of
AGND − 100 mV can be accommodated on the analog inputs
without degradation in performance, but leakage current increases
appreciably with increasing temperature. In buffered mode, the
analog inputs can handle much larger source impedances, but
the absolute input voltage range is restricted to between AGND
+ 50 mV to AV
common-mode range. This means that in buffered mode, there
are some restrictions on the allowable gains for bipolar input
ranges. Care must be taken in setting up the common-mode
voltage and input voltage range so that these limits are not
exceeded; otherwise, there will be a degradation in linearity
performance.
In unbuffered mode, the analog inputs look directly into the 7 pF
input sampling capacitor, C
AIN3(+) = (AIN3 + 6 × VBIAS + V
AIN3(−) = V
HICOM
VBIAS
AIN3
DD
HICOM
1R
3R
− 1.5 V, which also places restrictions on the
Figure 13. AIN3 Input Structure
1R = 5kΩ
+ 0.75 × (VBIAS − V
6R
6R
SAMP
AIN3(+)
. The dc input leakage current in
AIN3(–)
HICOM
MUX
HICOM
)/8
DD
)
+ 30 mV. This
Rev. B | Page 25 of 52
this unbuffered mode is 1 nA maximum. As a result, the analog
inputs see a dynamic load that is switched at the input sample
rate (see Figure 14). This sample rate depends on master clock
frequency and selected gain. C
discharged to AIN(−) every input sample cycle. The effective
resistance of the switch, R
C
impedances every input sample cycle. Therefore, in unbuffered
mode, source impedances mean a longer charge time for C
and this may result in gain errors on the part. Table 26 shows
the allowable external resistance/capacitance values, for unbuffered
mode, such that no gain error to the 16-bit level is introduced
on the part. Note that these capacitances are total capacitances
on the analog input. This external capacitance includes 10 pF
from the pins and lead frame of the device.
Table 26. External R, C Combination for No 16-Bit Gain
Error on Low Level Input Channels (Unbuffered Mode Only)
Gain
1
2
4
8 to 128
Figure 15. External R, C Combination for No 16-Bit Gain Error on Low Level
SAMP
400
350
300
250
200
150
100
must be charged through R
50
AIN(+)
AIN(–)
0
0
0
368 kΩ
177.2 kΩ
82.8 kΩ
35.2 kΩ
Figure 14. Unbuffered Analog Input Structure
GAIN = 4
SWITCHING FREQUENCY DEPENDS ON
f
GAIN = 1
GAIN = 2
CLKIN
Input Channels (Unbuffered Mode Only)
AND SELECTED GAIN
50
90.6 kΩ
44.2 kΩ
21.2 kΩ
9.6 kΩ
10
EXTERNAL CAPACITANCE (pF)
R
SW
External Capacitance (pF)
SW
C
(7kΩ TYP)
(7pF)
, is typically 7 kΩ.
SAMP
100
54.2 kΩ
26.4 kΩ
12.6 kΩ
5.8 kΩ
SAMP
V
100
DD
SW
/2
is charged to AIN(+) and
GAIN = 8 TO 128
and any additional source
500
14.6 kΩ
7.2 kΩ
3.4 kΩ
1.58 Ω
FIRST
INTEGRATOR
HIGH INPUT
IMPEDANCE
>1G
1000
1000
8.2 kΩ
4 kΩ
1.94 kΩ
880 Ω
AD7707
10000
5000
2.2 kΩ
1.12 kΩ
540 Ω
240 Ω
SAMP