AD7660 Analog Devices, AD7660 Datasheet - Page 10

• Manufacturer Part Number: AD7660
• Manufacturer: Analog Devices

Specifications of AD7660

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 100kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7660
CIRCUIT INFORMATION
The AD7660 is a fast, low power, single-supply, precise 16-bit
analog-to-digital converter (ADC). The AD7660 is capable of
converting 100,000 samples per second (100 kSPS) and allows
power saving between conversions. When operating at 100 SPS,
for example, it consumes typically only 21 mW. This feature
makes the AD7660 ideal for battery-powered applications.
The AD7660 provides the user with an on-chip track-and-
hold, successive-approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
The AD7660 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP package or a 48-lead LFCSP package that com-
bines space savings and allows flexible configurations as either
serial or parallel interface. The AD7660 is pin-to-pin compatible
with the AD7664.
CONVERTER OPERATION
The AD7660 is a successive-approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The capacitive DAC consists
of an array of 16 binary weighted capacitors and an additional
LSB capacitor. The comparator’s negative input is connected to
a “dummy” capacitor of the same value as the capacitive
DAC array.
REFGND
INGND
REF
IN
32768C
16384C
MSB
Figure 3. ADC Simplified Schematic
4C
2C
–10–
65536C
C
During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND
via SW
input IN. Thus, the capacitor array is used as a sampling capaci-
tor and acquires the analog signal on IN input. Similarly, the
dummy capacitor acquires the analog signal on the INGND input.
When the acquisition phase is complete and the CNVST input
goes or is LOW, a conversion phase is initiated. When the con-
version phase begins, SW
capacitor array and the dummy capacitor are then disconnected
from the inputs and connected to the REFGND input. There-
fore, the differential voltage between IN and INGND captured
at the end of the acquisition phase is applied to the comparator
inputs, causing the comparator to become unbalanced.
By switching each element of the capacitor array between REFGND
or REF, the comparator input varies by binary weighted voltage
steps (V
these switches, starting with the MSB first, in order to bring the
comparator back into a balanced condition. After the comple-
tion of this process, the control logic generates the ADC output
code and brings BUSY output LOW.
LSB
C
A
. All independent switches are connected to the analog
REF
LSB
/2, V
SW
SW
REF
COMP
B
A
/4 . . . V
SWITCHES
CONTROL
CONTROL
CNVST
A
LOGIC
REF
and SW
/65536). The control logic toggles
OUTPUT
BUSY
CODE
B
are opened first. The
REV. D