AD7843 Analog Devices, AD7843 Datasheet - Page 4

• Manufacturer Part Number: AD7843
• Description: Touch Screen Digitizer
• Manufacturer: Analog Devices

Specifications of AD7843

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 125kSPS
• Interface: Ser
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: SOP

AD7843
Parameter
POWER REQUIREMENTS
1
2
3
4
5
TIMING SPECIFICATIONS
T
Table 2. Timing Specifications
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
DCLK
ACQ
1
2
3
4
5
6
7
8
9
10
11
12
Temperature range as follows: A Version: −40°C to +85°C.
See the Terminology section.
Guaranteed by design.
Sample tested @ 25°C to ensure compliance.
See the Power vs. Throughput Rate section.
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
Mark/space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.4 V or 2.0 V.
t
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
A
3
12
V
I
Power Dissipation
4
CC
= T
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated
CC
2
5
Normal Mode (f
Normal Mode (f
Normal Mode (Static)
Shutdown Mode (Static)
Normal Mode (f
Shutdown
(Specified Performance)
MIN
to T
MAX
, unless otherwise noted; V
Limit at T
10
2
1.5
10
60
60
200
200
60
10
10
200
0
200
200
SAMPLE
SAMPLE
5
SAMPLE
= 125 kSPS)
= 12.5 kSPS)
= 125 kSPS)
MIN
, T
1
MAX
AD7843A
2.7/3.6
380
170
150
1
1.368
3.6
Figure 2. Load Circuit for Digital Output Timing Specifications
CC
OUTPUT
= 2.7 V to 3.6 V, V
Unit
kHz min
MHz max
µs min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns max
PIN
TO
1
50pF
C
L
Rev. B | Page 4 of 20
200µA
200µA
REF
Description
Acquisition time
CS falling edge to First DCLK rising edge
CS falling edge to BUSY three-state disabled
CS falling edge to DOUT three-state disabled
DCLK high pulse width
DCLK low pulse width
DCLK falling edge to BUSY rising edge
Data setup time prior to DCLK rising edge
Data valid to DCLK hold time
Data access time after DCLK falling edge
CS rising edge to DCLK ignored
CS rising edge to BUSY high impedance
CS rising edge to DOUT high impedance
= 2.5 V.
Unit
V min/max
µA max
µA max
mW max
µW max
µA typ
µA typ
I
I
OL
OH
12
1.6V
, quoted in the timing characteristics is the true bus relinquish
CC
) and are timed from a voltage level of 1.6 V.
Test Conditions/Comments
Functional from 2.2 V to 5.25 V
Digital I/Ps = 0 V or V
V
V
V
V
V
CC
CC
CC
CC
CC
= 3.6 V, 240 µA typ
= 2.7 V, f
= 3.6 V
= 3.6 V
= 3.6 V
DCLK
= 200 kHz
CC