AD7708 Analog Devices, AD7708 Datasheet - Page 29

• Manufacturer Part Number: AD7708
• Description: 16-Bit 8/10-Channel, Low Voltage, Low Power, Sigma Delta ADC
• Manufacturer: Analog Devices

Specifications of AD7708

• Resolution (bits): 16bit
• # Chan: 10
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref/PGA Gain) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: SOIC,SOP

AD0C2
AD0C1
AD0C0
Filter Register (A3, A2, A1, A0 = 0, 0, 1, 1; Power-On Reset = 45Hex)
The Filter Register is an 8-bit register from which data can be read or to which data can be written. This register determines the
amount of averaging performed by the sinc filter. Table XVII outlines the bit designations for the Filter Register. FR7 through FR0
indicate the bit location, FR denoting the bits are in the Filter Register. FR7 denotes the first bit of the data stream. The number in
brackets indicates the power-on/reset default status of that bit. The number in this register is used to set the decimation factor and
thus the output update rate for the ADCs. The filter register cannot be written to by the user the ADC is active. The update rate is
used for the ADCs is calculated as follows:
where
f
f
SF
The allowable range for SF is 13 decimal to 255 decimal with chop enabled, and the allowable SF range when chop is disabled is 03
decimal to 255 decimal. Examples of SF values and corresponding conversion rate (f
It should be noted that optimum performance is obtained when operating with chop enabled. When chopping is enabled (CHOP = 0),
the filter register is loaded with FF HEX during a calibration cycle. With chop disabled (CHOP =1), the value in the filter register is
used during calibration.
SF (Dec)
03
13
69
255
ADC
MOD
= ADC Output Update Rate,
= Modulator Clock Frequency = 32.768 kHz,
= Decimal Value Written to SF Register.
S
F
F
7
R
(
7
) 0
RN2
RN1
RN0
S
SF (Hex)
03
0D
45
FF
F
F
Table XVI. ADC Control Register (ADCCON) Bit Designations (continued)
6
R
6
(
) 1
ADC Range Bits
Written by the user to select the ADC input range as follows
RN2
0
0
0
0
1
1
1
1
S
F
F
f
f
ADC
ADC
5
R
Table XVII. Filter Register Bit Designations
(
5
) 0
=
=
Table XVIII. Update Rate vs. SF Word
1
3
8
RN1
0
0
1
1
0
0
1
1
f
N/A
105.3
19.79
5.35
ADC
×
×
1
SF
f
MOD
(Hz)
S
×
F
CHOP Enabled CHOP
F
4
f
R
MOD
CHOP Enabled
(
4
) 0
RN0
0
1
0
1
0
1
0
1
CHOP Disabled CHOP
S
F
F
3
Selected ADC Input Range (VREF = 2.5 V)
± 20 mV
± 40 mV
± 80 mV
± 160 mV
± 320 mV
± 640 mV
± 1.28 V
± 2.56 V
(
R
t
N/A
9.52
50.34
186.77
ADC
(
3
) 0
(ms)
(
=
0
ADC
S
)
F
F
) and time (t
2
=
R
(
1
2
) 1
)
f
1365.33
315
59.36
16.06
ADC
ADC
S
F
F
AD7708/AD7718
(Hz)
1
R
) are shown in Table XVIII.
(
1
) 0
CHOP Disabled
S
F
F
0
R
(
0
) 1
3.17
t
0.732
16.85
62.26
ADC
(ms)