AD7671 Analog Devices, AD7671 Datasheet - Page 16

• Manufacturer Part Number: AD7671
• Manufacturer: Analog Devices

Specifications of AD7671

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip (Vref),Bip (Vref) x 2,Bip (Vref) x 4,Uni (Vref),Uni (Vref) x 2,Uni (Vref) x 4
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7671
POWER DISSIPATION
In Impulse Mode, the AD7671 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which allows a
significant power savings when the conversion rate is reduced,
as shown in Figure 10. This feature makes the AD7671 ideal for
very low power battery applications.
This does not take into account the power, if any, dissipated by
the input resistive scaler, which depends on the input voltage
range used and the analog input voltage even in Power-Down
Mode. There is no power dissipated when the 0 V to 2.5 V is used
or when both the analog input voltage is 0 V and a unipolar range,
0 V to 5 V or 0 V to 10 V, is used.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be driven
close to the power rails (i.e., DVDD and DGND) and OVDD
should not exceed DVDD by more than 0.3 V.
100000
10000
Figure 10. Power Dissipation vs. Sample Rate
1000
100
75
70
65
60
55
50
45
40
35
0.1
10
1
1
1
Figure 9. PSRR vs. Frequency
WARP/NORMAL
10
10
IMPULSE
100
SAMPLING RATE – SPS
FREQUENCY – kHz
100
1000
10000
1000
100000
1000000
10000
–16–
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7671 is controlled by the signal CNVST, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. The CNVST signal operates independently of CS
and RD signals.
In Impulse Mode, conversions can be automatically initiated. If
CNVST is held LOW when BUSY is LOW, the AD7671 controls
the acquisition phase and then automatically initiates a new conver-
sion. By keeping CNVST LOW, the AD7671 keeps the conversion
process running by itself. It should be noted that the analog input
has to be settled when BUSY goes LOW. Also, at power-up,
CNVST should be brought LOW once to initiate the conversion
process. In this mode, the AD7671 could sometimes run slightly
faster than the guaranteed limits in the Impulse Mode of
666 kSPS. This feature does not exist in Warp or Normal Modes.
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum over-
shoot and undershoot or ringing. It is a good thing to shield the
CNVST trace with ground and also to add a low value serial
resistor (i.e., 50 W) termination close to the output of the
component that drives this line.
For applications where the SNR is critical, the CNVST signal
should have a very low jitter. To achieve this, some use a dedicated
oscillator for CNVST generation, or at least to clock it with a
high frequency low jitter clock as shown in Figure 5.
CNVST
MODE
BUSY
DATA BUS
CNVST
RESET
BUSY
ACQUIRE
t
t
3
5
Figure 11. Basic Conversion Timing
Figure 12. RESET Timing
t
CONVERT
1
t
7
t
4
t
9
t
t
2
6
ACQUIRE
t
8
t
8
REV. B
CONVERT