AD9874 Analog Devices, AD9874 Datasheet - Page 9

• Manufacturer Part Number: AD9874
• Description: Low Power IF Digitizing Subsystem
• Manufacturer: Analog Devices

Specifications of AD9874

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 26MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, f
T
TPC 4a. CDF of Maximum VGA
Attenuation Clip Point (VDDx = 3.0 V,
High Bias
TPC 5a. CDF of Minimum VGA
Attenuation Clip Point (VDDx = 3.0 V,
High Bias
1
2
3
REV. A
Data taken with Toko FSLM series 10 µH inductors.
High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01.
Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01.
A
= 25 C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)
100
100
100
TPC 6a. CDF of Supply Current
(VDDx = 3.0 V, High Bias
80
60
40
20
80
60
40
20
80
60
40
20
0
0
0
18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0
–31.6
–40 C
–19.4 –19.2 –19.0 –18.8 –18.6 –18.4
2
–40 C
2
)
)
–31.4 –31.2 –31.0 –30.8 –30.6 –30.4
SUPPLY CURRENT – mA
IFIN CLIP POINT – dBm
IFIN CLIP POINT – dBm
–40 C
+25 C
+25 C
+85 C
+25 C
+85 C
2
+85 C
)
TPC 4b. Maximum VGA Attenuation
Clip Point vs. Supply (High Bias
TPC 5b. Minimium VGA Attenuation
Clip Point vs. Supply (High Bias
–30.5
–31.5
–17.5
–18.0
–18.5
–19.0
–19.5
–20.0
–20.5
–29.5
–30.0
–31.0
–32.0
16
14
12
10
TPC 6b. Supply Current vs. f
(VDDx = 3.0 V, High Bias
2.7
2.7
8
6
4
2
0
13
(IDDD, IDDC, AND IDDL)
(IDDA, IDDF, AND IDDI)
15
DIGITAL
ANALOG
17
3.0
3.0
–9–
f
VDDx – V
VDDx – V
CLK
19
+25 C
DIGITAL INTERFACE
– MHz
+85 C
–40 C
21
3.3
3.3
(IDDH)
CLK
23
2
+85 C
+25 C
–40 C
)
= 18 MSPS, f
2
2
)
)
25
CLK
3.6
3.6
IF
TPC 4c. Maximum VGA Attenuation
Clip Point vs. Supply (Low Bias
TPC 5c. Minimium VGA Attenuation
Clip Point vs. Supply (Low Bias
= 109.56 MHz, f
TPC 6c. Supply Current vs. Supply
(High Bias
–17.5
–18.0
–18.5
–19.0
–19.5
–20.0
–20.5
–29.5
–30.0
–30.5
–31.0
–31.5
–32.0
18
16
14
12
10
2.7
2.7
8
6
4
2
0
2.7
2
)
LO
(IDDA, IDDF, AND IDDI)
3.0
3.0
= 107.4 MHz,
3.0
1
(IDDD, IDDC, AND IDDL)
VDDx – V
VDDx – V
VDDx – V
ANALOG
+85 C
+25 C
–40 C
DIGITAL INTERFACE
DIGITAL
AD9874
3.3
3.3
3.3
(IDDH)
+85 C
+25 C
–40 C
3
3
)
)
3.6
3.6
3.6