AD7677 Analog Devices, AD7677 Datasheet

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AD7677

Manufacturer Part Number
AD7677
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD7677

Resolution (bits)
16bit
# Chan
1
Sample Rate
1MSPS
Interface
Par,Ser
Analog Input Type
Diff-Uni
Ain Range
(2Vref) p-p
Adc Architecture
SAR
Pkg Type
CSP,QFP

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a
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
GENERAL DESCRIPTION
The AD7677 is a 16-bit, 1 MSPS, charge redistribution SAR,
fully differential, analog-to-digital converter that operates from a
single 5 V power supply. The part contains a high speed 16-bit
sampling ADC, an internal conversion clock, error correction
circuits, and both serial and parallel system interface ports.
The AD7677 is hardware factory calibrated and comprehen-
sively tested to ensure such ac parameters as signal-to-noise
ratio (SNR) and total harmonic distortion (THD), in addition
to the more traditional dc parameters of gain, offset, and linearity.
It features a very high sampling rate mode (Warp); a fast
mode (Normal) for asynchronous conversion rate applica-
tions; and, for low power applications, a reduced power mode
(Impulse) where the power is scaled with the throughput.
The AD7677 is available in a 48-lead LQFP or a tiny 48-lead
LFCSP with operation specified from –40°C to +85°C.
REV. A
FEATURES
Throughput: 1 MSPS
INL:
16 Bits Resolution with No Missing Codes
S/(N+D): 94 dB Typ @ 45 kHz
THD: –110 dB Typ @ 45 kHz
Differential Input Range:
Both AC and DC Specifications
No Pipeline Delay
Parallel (8 Bits/16 Bits) and Serial 5 V/3 V Interface
Single 5 V Supply Operation
115 mW Typical Power Dissipation, 15 W @ 100 SPS
Power-Down Mode: 7 W Max
Packages: 48-Lead Quad Flatpack (LQFP)
Pin-to-Pin Compatible Upgrade of the AD7664/AD7675/
APPLICATIONS
CT Scanners
Data Acquisition
Instrumentation
Spectrum Analysis
Medical Instruments
Battery-Powered Systems
Process Control
48-Lead Frame Chip Scale (LFCSP)
AD7676
1 LSB Max ( 0.0015% of Full Scale)
2.5 V
Type/kSPS
Pseudo
Differential
True Bipolar
True Differential
PRODUCT HIGHLIGHTS
1. Excellent INL
2. Superior AC Performances
3. Fast Throughput
4. Single-Supply Operation
5. Serial or Parallel Interface
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
RESET
The AD7677 has a maximum integral nonlinearity of 1 LSB
with a no missing 16-bit code.
The AD7677 has a minimum dynamic of 92 dB, 94 dB typical.
The AD7677 is a 1 MSPS, charge redistribution, 16-bit SAR
ADC with internal error correction circuitry.
The AD7677 operates from a single 5 V supply and typically
dissipates only 115 mW. Its power dissipation decreases
with the throughput. It consumes 7 µW maximum when in
power-down.
Versatile parallel (8 bits or 16 bits) or 2-wire serial inter-
face arrangement compatible with both 3 V or 5 V logic.
IN+
IN–
PD
AVDD AGND REF REFGND
AD7677
WARP
CALIBRATION CIRCUITRY
16-Bit, 1 LSB INL, 1 MSPS
FUNCTIONAL BLOCK DIAGRAM
CONTROL LOGIC AND
IMPULSE
SWITCHED
CAP DAC
100–250
AD7660
AD7663
AD7675
PulSAR Selection
CNVST
CLOCK
Differential ADC
500–570
AD7650
AD7664
AD7665
AD7676
DVDD
© Analog Devices, Inc., 2002
INTERFACE
PARALLEL
SERIAL
PORT
AD7677
DGND
www.analog.com
16
1000
AD7671
AD7677
OVDD
OGND
SER/PAR
BUSY
DATA[15:0]
CS
RD
OB/2C
BYTESWAP

Related parts for AD7677

AD7677 Summary of contents

Page 1

... Excellent INL The AD7677 has a maximum integral nonlinearity of 1 LSB with a no missing 16-bit code. 2. Superior AC Performances The AD7677 has a minimum dynamic typical. 3. Fast Throughput The AD7677 MSPS, charge redistribution, 16-bit SAR ADC with internal error correction circuitry. ...

Page 2

... AD7677–SPECIFICATIONS Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate Time Between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error ...

Page 3

... Contact factory for extended temperature range. Specifications subject to change without notice. REV. A Conditions Min 4.75 4.75 2.7 1 MSPS Throughput 7 666 kSPS Throughput 7 100 SPS Throughput 2 1 MSPS Throughput –40 MIN MAX –3– AD7677 Typ Max Unit 5.25 V 16.7 mA 6.4 mA µ µ ...

Page 4

... AD7677 TIMING SPECIFICATIONS Refer to Figures 11 and 12 Convert Pulsewidth Time Between Conversions (Warp Mode/Normal Mode/Impulse Mode) CNVST LOW to BUSY HIGH Delay BUSY HIGH All Modes Except in Master Serial Read after Convert Mode (Warp Mode/Normal Mode/Impulse Mode) Aperture Delay End of Conversion to BUSY LOW Delay ...

Page 5

... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7677 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

Page 6

... AD7677 Pin No. Mnemonic Type Description 1 AGND P Analog Power Ground Pin 2 AVDD P Analog Power Pin. Nominally Connect 40–42, 44–48 4 BYTESWAP DI Parallel Mode Selection (8-bit/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0] ...

Page 7

... Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled also used to gate the external serial clock. Reset Input. When set to a logic HIGH, reset the AD7677. Current conversion if any is aborted. Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver- sions are inhibited after the current one is completed ...

Page 8

... Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. TRANSIENT RESPONSE The time required for the AD7677 to achieve its rated accuracy after a full-scale step function is applied to its input. –8– 36 ...

Page 9

... TPC 2. Histogram of 16,384 Conversions Input at the Code Transition 0.0 0.1 0.2 0.3 0.4 0.5 0.6 POSITIVE INL – LSB TPC 3. Typical Positive INL Distribution (199 Units) REV. A Typical Performance Characteristics–AD7677 1.00 0.75 0.50 0.25 0.00 –0.25 –0.50 –0.75 –1.00 49152 65536 TPC 4. Differential Nonlinearity vs. Code 16000 14000 12000 10000 8000 ...

Page 10

... AD7677 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 0 100 200 300 FREQUENCY – kHz TPC 7. FFT Plot 100 95 SNR 100 FREQUENCY – kHz TPC 8. SNR, S/(N+D), and ENOB vs. Frequency –60 –50 –40 –30 –20 INPUT LEVEL – dB TPC 9 ...

Page 11

... ADC that does not exhibit any pipe- line or latency, making it ideal for multiple multiplexed channel applications. The AD7677 can be operated from a single 5 V supply and be interfaced to either digital logic housed in a 48-lead LQFP package that combines space savings and flexible configurations as either serial or parallel interface ...

Page 12

... TYPICAL CONNECTION DIAGRAM Figure 5 shows a typical connection diagram for the AD7677. Different circuitry shown on this diagram is optional and is discussed below. Analog Inputs Figure 6 shows a simplified analog input section of AD7677. DVDD 100 ...

Page 13

... If the application can tolerate more noise, the AD8138 can be used. Driver Amplifier Choice Although the AD7677 is easy to drive, the driver amplifier needs to meet at least the following requirements: • The driver amplifier and the AD7677 analog input circuit have to be able together to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). In the amplifier’ ...

Page 14

... FREQUENCY – Hz Figure 9. PSRR vs. Frequency Power Supply The AD7677 uses three sets of power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.7 V and DVDD +0 ...

Page 15

... The serial interface is multiplexed on the parallel databus. The AD7677 digital interface also accommodates both REV. A logic by simply connecting the OVDD supply pin of the AD7677 to the host system interface digital supply. Finally, by using the OB/2C input pin, both two’s complement or straight binary coding can be used ...

Page 16

... AD7677 The BYTESWAP pin allows a glueless interface to an 8-bit bus. As shown in Figure 16, the LSB byte is output on D[7:0] and the MSB is output on D[15:8] when BYTESWAP is low. When BYTESWAP is high, the LSB and MSB bytes are swapped and the LSB is output on D[15:8] and the MSB is output on D[7:0]. ...

Page 17

... Internal Clock The AD7677 is configured to generate and provide the serial data clock SCLK when the EXT/INT Pin is held low. The AD7677 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted if desired ...

Page 18

... Figure 19 and Figure 20 show the detailed timing diagrams of these methods. While the AD7677 is performing a bit decision important that voltage transients not occur on digital input/output pins or degra- dation of the conversion result could occur. This is particularly ...

Page 19

... This facilitates the use of ground planes that can be easily separated. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7677 least as close as possible to the AD7677. If the AD7677 system where multiple devices require analog to digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7677 ...

Page 20

... AD7677 1.45 1.40 1.35 0.15 0.05 ROTATED 90 CCW BSC SQ PIN 1 INDICATOR 1.00 12 MAX 0.90 0.80 0.25 REF SEATING PLANE Revision History Location 7/02—Data Sheet changed from REV REV. A. Added 48-Lead LFCSP to FEATURES and GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Added PulSAR Selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Edits to NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additions to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Edits to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Changes to Power Supply section ...

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