AD7477A Analog Devices, AD7477A Datasheet - Page 22

• Manufacturer Part Number: AD7477A
• Description: 10-Bit, 1 MSPS, Low-Power A/D Converter in SC70 and MSOP Packages
• Manufacturer: Analog Devices

Specifications of AD7477A

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SC70,SOP

AD7476A/AD7477A/AD7478A
CS going low clocks out the first leading zero to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges beginning with the
second leading zero. Thus, the first falling clock edge on the
serial clock has the first leading zero provided and also clocks
out the second leading zero. For the AD7476A, the final bit in
the data transfer is valid on the 16th falling edge, having been
clocked out on the previous (15th) falling edge.
In applications with a slower SCLK, it is possible to read in data
on each SCLK rising edge. In this case, the first falling edge of
SCLK clocks out the second leading zero, which can be read in
the first rising edge. However, the first leading zero that was
clocked out when CS went low will be missed, unless it was not
read in the first falling edge. The 15th falling edge of SCLK clocks
out the last bit and it can be read in the 15th rising SCLK edge.
If CS goes low just after one SCLK falling edge has elapsed, CS
clocks out the first leading zero as it did before, and it can be
read in the SCLK rising edge. The next SCLK falling edge clocks
out the second leading zero, and it can be read in the following
rising edge.
SDATA
THREE-STATE
SCLK
CS
t
2
Z
1
ZERO
4 LEADING ZEROS
2
ZERO
Figure 27. AD7478A in a 12 SCLK Cycle Serial Interface
3
ZERO
10.5(1/
t
CONVERT
4
f
SCLK
1/THROUGHPUT
DB7
Rev. F | Page 22 of 28
)
5
DB6
AD7478A IN A 12 SCLK CYCLE SERIAL INTERFACE
For the AD7478A, if CS is brought high in the 12th rising edge
after four leading zeros and eight bits of the conversion have
been provided, the part can achieve a 1.2 MSPS throughput
rate. For the AD7478A, the track-and-hold goes back into track
in the 11th rising edge. In this case, a f
throughput of 1.2 MSPS give a cycle time of
With t
satisfies the requirement of 225 ns for t
From Figure 27, t
where t
This allows a value of 237 ns for t
requirement of 50 ns.
t
0.5 (1/f
2
11
2
+ 10.5(1/f
8
= 10 ns min, this leaves t
B
= 36 ns maximum.
DB0
SCLK
t
8
12
) + t
SCLK
ACQ
8
)+ t
THREE-STATE
+ t
is comprised of
ACQ
QUIET
t
ACQ
t
QUIET
= 833 ns
t
1
ACQ
QUIET
to be 298 ns. This 298 ns
, satisfying the minimum
SCLK
ACQ
.
= 20 MHz and a