AD7904 Analog Devices, AD7904 Datasheet - Page 9

• Manufacturer Part Number: AD7904
• Description: 4-Channel, 1 MSPS, 8-Bit A/D Converter with Sequencer in 16-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7904

• Resolution (bits): 8bit
• # Chan: 4
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: SOP

TIMING SPECIFICATIONS
AV
Table 4.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
SCLK
CONVERT
QUIET
2
3
4
5
6
7
8
9
10
11
12
Sample tested @ 25°C to ensure compliance. All input signals are specified with t
The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
Mark/space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × V
t
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
3
4
8
3
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
DD
2
= 2.7 V to 5.25 V, V
1
AV
10
20
16 × t
50
10
35
40
0.4 × t
0.4 × t
10
15/45
10
5
20
1
DD
= 3 V
SCLK
SCLK
SCLK
DRIVE
≤ AV
Limit at T
AV
10
20
16 × t
50
10
30
40
0.4 × t
0.4 × t
10
15/35
10
5
20
1
DD
DD
, REF
= 5 V
SCLK
SCLK
SCLK
MIN
IN
Figure 2. Load Circuit for Digital Output Timing Specifications
, T
= 2.5 V, T
MAX
Unit
kHz min
MHz max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min/ns max
ns min
ns min
ns min
μs max
OUTPUT
PIN
TO
A
= T
50pF
C
MIN
Rev. B | Page 9 of 32
L
to T
200µA
200µA
R
= t
Description
Minimum quiet time required between the CS rising edge and the start
of the next conversion
CS to SCLK setup time
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to DOUT valid hold time
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
16th SCLK falling edge to CS high
Power-up time from full shutdown/auto shutdown modes
MAX
F
= 5 ns (10% to 90% of AV
, unless otherwise noted.
I
I
OL
OH
1.6V
8
, quoted in the timing characteristics is the true bus relinquish
DD
) and timed from a voltage level of 1.6 V (see Figure 2).
DRIVE
.
AD7904/AD7914/AD7924