AD9878 Analog Devices, AD9878 Datasheet - Page 6

• Manufacturer Part Number: AD9878
• Description: Low Cost, 3.3 V, CMOS Mixed Signal Front End (MxFE®) for Broadband Applications
• Manufacturer: Analog Devices

Specifications of AD9878

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 29MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: QFP

AD9878
PARAMETER
TIMING CHARACTERISTICS (10 pF Load)
SERIAL CONTROL BUS
CMOS LOGIC INPUTS
CMOS LOGIC OUTPUTS (1 mA Load)
POWER SUPPLY
Wake-Up Time
Minimum RESET Pulse Width Low, t
Digital Output Rise/Fall Time
Tx/Rx Interface
REFCLK Rising or Falling Edge to
REFCLK Edge to MCLK Falling Edge, t
Maximum SCLK Frequency, f
Minimum Clock Pulse Width High, t
Minimum Clock Pulse Width Low, t
Maximum Clock Rise/Fall Time
Minimum Data/Chip-Select Setup Time, t
Minimum Data Hold Time, t
Maximum Data Valid Time, t
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Supply Current, I
Supply Current, I
Power Supply Rejection (Differential Signal)
RxSYNC Valid Delay, t
MCLK Frequency, f
TxSYNC/TxIQ Setup Time, t
TxSYNC/TxIQ Hold Time, t
MCLK Rising Edge to RxSYNC Valid Delay, t
Analog Supply Current, I
Digital Supply Current, I
Standby (PWRDN Pin Active, I
Full Power-Down (Register 0x02 = 0xFF)
Power-Down Tx Path (Register 0x02 = 0x60)
Power-Down IF12 Rx Path (Register 0x02 = 0x1B)
Tx DAC
10-Bit ADC
12-Bit ADC
S
S
(Full Operation)
MCLK
OD
DS
AS
DH
HU
DV
SCLK
SU
AS
+ I
PWL
RL
PWH
DS
EE
)
DS
MD
Temp
N/A
N/A
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Rev. A | Page 6 of 36
Test Level
N/A
N/A
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
II
III
II
II
II
III
III
II
II
III
III
III
III
III
Min
5
2.8
3
3
0
t
4 − 2.0
−1.0
30
30
25
0
V
V
OSCIN
DRVDD
DRVDD
/
− 0.7
− 0.6
Typ
3
184
105
79
124
46
124
131
<0.25
<0.0001
<0.0004
Max
200
4
58
1.0
t
4 + 3.0
+1.0
15
1
30
0.4
12
12
0.4
204
115
89
137
52
159
OSCIN
/
t
t
ns
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
µs
ns
ns
ns
V
V
µA
µA
pF
V
V
mA
mA
mA
mA
mA
mA
mA
% FS
% FS
% FS
Unit
MCLK
MCLK
cycles
cycles