AD7467 Analog Devices, AD7467 Datasheet - Page 9

• Manufacturer Part Number: AD7467
• Description: 1.6 V Micro-Power 10-Bit ADC
• Manufacturer: Analog Devices

Specifications of AD7467

• Resolution (bits): 10bit
• # Chan: 1
• Sample Rate: 200kSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOP,SOT

TIMING SPECIFICATIONS
For all devices, V
signals are specified with tr = tf = 5 ns (10% to 90% of V
Table 4.
Parameter
f
t
Acquisition Time
t
t
t
t
t
t
t
t
t
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
DD
= 1.6 V to 3.6 V; T
Limit at T
3.4
10
20
150
16 × t
12 × t
10 × t
780
640
10
10
55
55
140
0.4 t
0.4 t
10
60
7
SCLK
SCLK
SCLK
SCLK
SCLK
MIN
, T
MAX
A
= T
Unit
MHz max
kHz min
kHz min
kHz min
ns max
ns max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
MIN
Figure 2. Load Circuit for Digital Output Timing Specifications
to T
TO OUTPUT
MAX
, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input
DD
V
V
AD7466.
AD7467.
AD7468.
Acquisition time/power-up time from power-down. See the Terminology section.
The acquisition time is the time required for the part to acquire a full-scale step
input value within ±1 LSB or a 30 kHz ac input value within ±0.5 LSB.
Minimum quiet time required between bus relinquish and the start of the next
conversion.
Minimum CS pulse width.
CS to SCLK setup time. If V
minimum in order to meet the maximum figure for the acquisition time.
Delay from CS until SDATA is three-state disabled. Measured with the load circuit
in Figure 2 and defined as the time required for the output to cross the V
voltage.
Data access time after SCLK falling edge. Measured with the load circuit in Figure 2
and defined as the time required for the output to cross the V
SCLK to data valid hold time. Measured with the load circuit in Figure 2 and
defined as the time required for the output to cross the V
SCLK falling edge to SDATA three-state. t
by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The
measured number is then extrapolated back to remove the effects of charging or
discharging the 50 pF capacitor. This means that the time, t
characteristics, is the true bus relinquish time of the part, and is independent of
the bus loading.
Description
Mark/space ratio for the SCLK input is 40/60 to 60/40.
1.6 V ≤ V
V
1.8 V ≤ V
SCLK low pulse width.
SCLK high pulse width.
SCLK falling edge to SDATA three-state.
PIN
DD
DD
DD
) and timed from a voltage level of 1.4 V.
= 3.3 V; minimum f
= 3.6 V; minimum f
= 1.6 V.
50pF
Rev. C | Page 9 of 28
C
L
DD
DD
200μA
200μA
≤ 3 V; minimum f
≤ 3.6 V.
I
I
OL
OH
SCLK
SCLK
at which specifications are guaranteed.
at which specifications are guaranteed.
DD
1.4V
SCLK
= 1.6 V and f
at which specifications are guaranteed.
8
SCLK
is derived from the measured time taken
AD7466/AD7467/AD7468
= 3.4 MHz, t
2
IH
has to be 192 ns
or V
8
, quoted in the timing
IH
IL
or V
voltage.
IL
voltage.
IH
or V
IL