AD7651 Analog Devices, AD7651 Datasheet - Page 8

• Manufacturer Part Number: AD7651
• Manufacturer: Analog Devices

Specifications of AD7651

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 100kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: Uni (Vref),Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7651
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1, 36,
41, 42
2, 44
3, 6,
7, 40
4
5
8
9, 10
11, 12
13
14
15
Mnemonic
AGND
AVDD
NC
BYTESWAP
OB/2C
SER/PAR
D[0:1]
D[2:3]or
DIVSCLK[0:1]
D4 or
EXT/INT
D5 or
INVSYNC
D6 or
INVSCLK
Type
P
P
DI
DI
DI
DO
DI/O
DI/O
DI/O
DI/O
1
Description
Analog Power Ground Pin.
Input Analog Power Pin. Nominally 5 V.
No Connect.
Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on
D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary;
when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift
register.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial
interface mode is selected and some bits of the DATA bus are used as a serial port.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high
impedance.
When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert),
these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that
clocks the data output. In other serial modes, these pins are not used.
When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing
the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected
on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external
clock signal connected to the SCLK input.
When SER/PAR is LOW, this output is used as Bit 5 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC
signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When HIGH,
SYNC is active LOW.
When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active
in both master and slave modes.
NC = NO CONNECT
D2/DIVSCLK0
D3/DIVSCLK1
Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)
BYTESWAP
SER/PAR
OB/2C
AGND
AVDD
NC
NC
NC
D0
D1
10
11
12
1
2
3
4
5
6
7
8
9
48 47 46 45 44
13 14 15 16 17 18 19 20 21 22 23 24
PIN 1
IDENTIFIER
Rev. 0 | Page 8 of 28
(Not to Scale)
TOP VIEW
AD7651
43 42 41 40
39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
02965-0-002
AGND
CNVST
PD
RESET
CS
RD
DGND
BUSY
D15
D14
D13
D12