AD7787 Analog Devices, AD7787 Datasheet - Page 13

• Manufacturer Part Number: AD7787
• Description: Low Power, 2-Channel 24-Bit Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD7787

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Bip,SE-Uni
• Ain Range: (2Vref) p-p,(Vref) p-p,Uni (Vref)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

FILTER REGISTER (RS1, RS0 = 1, 0; POWER-ON/RESET = 0×04)
The filter register is an 8-bit register from which data can be read or to which data can be written. This register is used to set the output
word rate. Table 11 outlines the bit designations for the filter register. FR0 through FR7 indicate the bit locations, FR denoting the bits are
in the filter register. FR7 denotes the first bit of the data stream. The number in the parenthesis indicates the power-on/reset default status
of that bit.
FR7
0 (0)
Table 11. Filter Register Bit Designations
Bit
Location
FR7 to
FR6
FR5 to
FR4
FR3
FR2 to
FR0
Table 12. Update Rates
FS2
0
0
0
0
1
1
1
1
DATA REGISTER (RS1, RS0 = 1, 1; POWER-ON/RESET = 0×000000)
The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from
this register, the RDY bit/pin is set.
FS1
0
0
1
1
0
0
1
1
Bit Name
0
CLKDIV1
to CDIV0
0
FS2 to FS0
FR6
0 (0)
FS0
0
1
0
1
0
1
0
1
FR5
CDIV1 (0)
Description
These bits must be programmed with a Logic 0 for correct operation.
These bits are used to operate the AD7787 in the lower power modes. The clock is internally divided and the
power is reduced. In the low power modes, the update rates will scale with the clock frequency so that dividing
the clock by 2 causes the update rate to be reduced by a factor of 2 also.
00
01
10
11
This bit must be programmed with a Logic 0 for correct operation.
These bits set the output word rate of the ADC. The update rate influences the 50 Hz/60 Hz rejection and the
noise. Table 12 shows the allowable update rates when normal power mode is used. In the low power modes,
the update rate is scaled with the clock frequency. For example, if the internal clock is divided by a factor of 2,
the corresponding update rates are divided by 2 also.
f
120
100
33.3
20
16.6
16.7
13.3
9.5
ADC
(Hz)
Normal Mode
Clock Divided by 2
Clock Divided by 4
Clock Divided by 8
f3dB (Hz)
28
24
8
4.7
4
4
3.2
2.3
FR4
CDIV0 (0)
RMS Noise (µV)
40
25
3.36
1.6
1.5
1.5
1.2
1.1
Rev. 0 | Page 13 of 20
FR3
0 (0)
Rejection
65 dB @ 50 Hz/60 Hz (Default Setting)
67 dB @ 50 Hz/60 Hz
25 dB @ 60 Hz
25 dB @ 50 Hz
80 dB @ 60 Hz
80 dB @ 50 Hz
FR2
FS2 (1)
FR1
FS1 (0)
FR0
FS0 (0)
AD7787