AD9481 Analog Devices, AD9481 Datasheet - Page 6

• Manufacturer Part Number: AD9481
• Description: 8-Bit, 250 MSPS, 3.3 V A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9481

• Resolution (bits): 8bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,1 V p-p
• Adc Architecture: Pipelined
• Pkg Type: QFP

AD9481
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V; differential encode input, duty cycle stabilizer enabled, unless otherwise noted.
Table 4.
Parameter
CLOCK
OUTPUT PARAMETERS
APERTURE
OUT-OF-RANGE RECOVERY TIME
1
2
3
4
5
C
Valid time is approximately equal to minimum t
T
Data changing to (DCO+ or DCO−) rising edge delay.
T
CPD
SKA
LOAD
Maximum Conversion Rate
Minimum Conversion Rate
Clock Pulse-Width High (t
Clock Pulse-Width Low (t
DS Input Setup Time (t
DS Input Hold Time (t
Valid Time (t
Propagation Delay (t
Rise Time (t
Fall Time (t
DCO Propagation Delay (t
Data-to-DCO Skew (t
A Port Data to DCO− Rising (t
B Port Data to DCO+ Rising (t
Pipeline Latency (A, B)
Aperture Delay (t
Aperture Uncertainty (Jitter)
, T
equals clock rising edge to DCO (+ or −) rising edge delay.
equals 5 pF maximum for all output switching specifications.
SKB
are both clock rate dependent delays equal to T
F
R
) 10% to 90%
) 10% to 90%
V
)
2
A
)
1
PD
PD
HDS
)
SDS
− t
)
EL
)
EH
CPD
CPD
)
)
)
)
SKB
4
SKA
3
)
)
5
PD
.
CYCLE
− (Data to DCO skew).
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
Rev. 0 | Page 6 of 28
Test Level
VI
IV
IV
IV
IV
IV
VI
VI
V
V
VI
VI
IV
IV
IV
V
V
V
Min
250
1.2
1.2
0.5
0.5
2.5
2.5
−0.5
AD9481-250
Typ
2
2
4
670
360
3.9
4
4
8
1.5
0.25
1
Max
20
5.4
5.3
+0.5
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
Cycles
ns
ps rms
Cycle