AD7998 Analog Devices, AD7998 Datasheet - Page 21

• Manufacturer Part Number: AD7998
• Description: 8-Channel, 12-Bit ADC with I2C Compatible Interface in 20-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7998

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 79kSPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: SOP

Hysteresis Register (CH1/CH2/CH3/CH4)
Each hysteresis register is a 16-bit read/write register, of which
only the 12 LSBs are used. The hysteresis register stores the
hysteresis value, N, when using the limit registers. Each pair of
limit registers has a dedicated hysteresis register. The hysteresis
value determines the reset point for the ALERT pin/Alert_Flag
if a violation of the limits has occurred. For example, if a
hysteresis value of 8 LSBs is required on the upper and lower
limits of Channel 1, the 12-bit word, 0000 0000 0000 1000,
should be written to the hysteresis register of CH1, the address
of which is shown in Table 8. On power-up, the hysteresis
registers contain a value of 2 for the AD7997 and a value of 8
for the AD7998. If a different hysteresis value is required, that
value must be written to the hysteresis register for the channel
in question. For the AD7997, D1 and D0 of the hysteresis
register should contain 0s.
Table 19. Hysteresis Register (First Read/Write)
D15
0
Table 20. Hysteresis Register (Second Read/Write)
D7
B7
Using the Limit Registers to Store Min/Max Conversion
Results for CH1 to CH4
If full scale, that is, all 1s, is written to the hysteresis register for
a particular channel, the DATA
that channel no longer act as limit registers as previously
described, but instead act as storage registers for the maximum
and minimum conversion results returned from conversions on
a channel over any given period of time. This function is useful
in applications where the widest span of actual conversion
results is required rather than using the ALERT to signal that an
intervention is necessary. This function could be useful for
monitoring temperature extremes during refrigerated goods
transportation. It must be noted that on power-up, the contents
of the DATA
contents of the DATA
Therefore, minimum and maximum conversion values being
stored in this way are lost if power is removed or cycled.
D14
0
D6
B6
HIGH
D13
0
D5
B5
register for each channel are full scale, while the
LOW
registers are zero scale by default.
D12
0
D4
B4
HIGH
D11
B11
D3
B3
and DATA
D10
B10
D2
B2
LOW
registers for
D9
B9
D1
B1
D8
B8
D0
B0
Rev. 0 | Page 21 of 32
ALERT STATUS REGISTER (CH1 TO CH4)
The alert status register is an 8-bit, read/write register that
provides information on an alert event. If a conversion result
activates the ALERT pin or the Alert_Flag bit in the conversion
result register, as described in the Limit Registers section, the
alert status register may be read to gain further information.
The Alert Status Register contains two status bits per channel,
one corresponding to the DATA
DATA
violation occurred—that is, on which channel—and whether
the violation occurred on the upper or lower limit. If a second
alert event occurs on the other channel between receiving the
first alert and interrogating the alert status register, the
corresponding bit for that alert event is also set.
The alert status register only contains information for CH1 to
CH4 because these are the only channels with associated limit
registers.
The entire contents of the alert status register can be cleared by
writing 1,1, to Bits D2 and D1 in the configuration register, as
shown in Table 12. This may also be done by writing all 1s to
the alert status register itself. Thus, if the alert status register is
addressed for a write operation, which is all 1s, the contents of
the alert status register are cleared or reset to all 0s.
Table 21. Alert Status Register
D7
CH4
Table 22. Alert Status Register Bit Function Description
Bit
D0
D1
D2
D3
D4
D5
D6
D7
HI
LOW
D6
CH4
limit. The bit with a status of 1 shows where the
LO
Mnemonic
CH1
CH1
CH2
CH2
CH3
CH3
CH4
CH4
D5
CH3
LO
HI
LO
HI
LO
HI
LO
HI
HI
D4
CH3
LO
If bit is set to 1, violation of…
DATA
No violation if bit is set to 0.
DATA
No violation if bit is set to 0.
DATA
No violation if bit is set to 0.
DATA
No violation if bit is set to 0.
DATA
No violation if bit is set to 0.
DATA
No violation if bit is set to 0.
DATA
No violation if bit is set to 0.
DATA
No violation if bit is set to 0.
HIGH
D3
CH2
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
limit and the other to the
HI
limit on Channel 1.
limit on Channel 2.
limit on Channel 3.
limit on Channel 4.
limit on Channel 1.
limit on Channel 2.
limit on Channel 3.
limit on Channel 4.
AD7997/AD7998
D2
CH2
LO
D1
CH1
HI
D0
CH1
LO