AD7939 Analog Devices, AD7939 Datasheet - Page 23

• Manufacturer Part Number: AD7939
• Description: 8-Channel, 1.5 MSPS, 10-Bit Parallel ADCs with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7939

• Resolution (bits): 10bit
• # Chan: 8
• Sample Rate: 1.5MSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,5V p-p,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

Data Sheet
Using the Sequencer: Programmable Sequence
(SEQ = 0, SHDW = 1)
The AD7938/AD7939 can be configured to automatically cycle
through a number of selected channels using the on-chip
programmable sequencer by setting SEQ = 0 and SHDW = 1 in
the control register. The analog input channels to be converted
are selected by setting the relevant bits in the shadow register
to 1 (see Table 12).
Once the shadow register has been programmed with the
required sequence, the next conversion executed is on the
lowest channel programmed in the SHDW register. The next
conversion executed is on the next highest channel in the
sequence and so on. When the last channel in the sequence
is converted, the internal multiplexer returns to the first
channel selected in the shadow register and commences the
sequence again.
It is not necessary to write to the control register again once a
sequencer operation has been initiated. The WR input must be
kept high to ensure that the control register is not accidentally
overwritten or that a sequence operation is not interrupted. If
the control register is written to at any time during the sequence,
ensure that the SEQ and SHDW bits are set to 1, 0 to avoid
interrupting the conversion sequence. The sequence program
remains in force until such time as the AD7938/AD7939 is
written to and the SEQ and SHDW bits are configured with any
bit combination except 1, 0. Figure 32 shows a flow chart of the
programmable sequence operation.
THIS WRITE CYCLE IS TO PROGRAM THE SHADOW REGISTER.
WITH EACH CONVST PULSE.
IN THE SHADOW REGISTER
CONTINUOUSLY CONVERT
CHANNELS SELECTED
THE CHANNELS TO BE INCLUDED IN THE SEQUENCE.
CONSECUTIVE
Figure 32. Programmable Sequence Flow Chart
SET UP OPERATING MODE, ANALOG INPUT
SHDW BIT = 1
WRITE TO THE CONTROL REGISTER TO
SEQ BIT = 0
WR = HIGH
SET RELEVANT BITS TO SELECT
AND OUTPUT CONFIGURATION
INITIATE A WRITE CYCLE.
SET SEQ = 0 SHDW = 1.
POWER ON
CODING, ANALOG INPUT TYPE,
WITH EACH CONVST PULSE
REGISTER TO BE CHANGED
ETC BITS IN THE CONTROL
CONTINUOUSLY CONVERT
BUT ALLOWS THE RANGE,
WITHOUT INTERRUPTING
SEQ BIT = 1
SHDW BIT = 0
CHANNELS SELECTED
THE SEQUENCE.
CONSECUTIVE
Rev. C | Page 23 of 36
Consecutive Sequence (SEQ = 1, SHDW = 1)
A sequence of consecutive channels can be converted beginning
with Channel 0 and ending with a final channel selected by
writing to the ADD2 to ADD0 bits in the control register. This
is done by setting the SEQ and SHDW bits in the control
register to 1. In this mode, the sequencer can be used without
having to write to the shadow register. To set this mode up, the
next conversion, once the control register is written to, is on
Channel 0, then Channel 1, and so on, until the channel
selected by the address bits (ADD2 to ADD0) is reached. The
cycle begins again provided the WR input is tied high. If low,
the SEQ and SHDW bits must be set to 1, 0 to allow the ADC to
continue its preprogrammed sequence uninterrupted. Figure 33
shows the flowchart of the consecutive sequence mode.
REFERENCE
The AD7938/AD7939 can operate with either the on-chip
reference or external reference. The internal reference is
selected by setting the REF bit in the internal control register
to 1. A block diagram of the internal reference circuitry is
shown in Figure 34. The internal reference circuitry includes an
on-chip 2.5 V band gap reference and a reference buffer. When
using the internal reference, the V
decoupled to AGND with a 0.47 μF capacitor. This internal
reference not only provides the reference for the analog-to-
digital conversion, but it can also be used externally in the
system. It is recommended that the reference output is buffered
using an external precision op amp before applying it anywhere
in the system.
Figure 34. Internal Reference Circuit Block Diagram
Figure 33. Consecutive Sequence Mode Flow Chart
V
V
REFOUT
REFIN
SELECTED FINAL CHANNEL ON ADD2 TO ADD0
SEQUENCE OF CHANNELS FROM CHANNEL 0
CONTINUOUSLY CONVERT A CONSECUTIVE
SET UP OPERATING MODE, ANALOG INPUT
UP TO AND INCLUDING THE PREVIOUSLY
ALLOWS THE RANGE, CODING, ANALOG
WRITE TO THE CONTROL REGISTER TO
AND OUTPUT CONFIGURATION SELECT
/
CONTROL REGISTER TO BE CHANGED
CONSECUTIVE CHANNELS SELECTED
FINAL CHANNEL (ADD2 TO ADD0) IN
WITH EACH CONVST PULSE BUT
INPUT TYPE, ETC. BITS IN THE
WITH EACH CONVST PULSE.
CONSECUTIVE SEQUENCE.
CONTINUOUSLY CONVERT
WITHOUT INTERRUPTING
SET SEQ = 1 SHDW = 1.
BUFFER
THE SEQUENCE.
POWER ON
ADC
SEQ BIT = 1
SHDW BIT = 0
REFIN
/V
AD7938/AD7939
REFERENCE
AD7938/
AD7939
REFOUT
pin should be