AD7877 Analog Devices, AD7877 Datasheet - Page 5

• Manufacturer Part Number: AD7877
• Description: Touch Screen Controller
• Manufacturer: Analog Devices

Specifications of AD7877

• Resolution (bits): 12bit
• # Chan: 9
• Sample Rate: 125kSPS
• Interface: Ser
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: CSP

Data Sheet
TIMING SPECIFICATIONS
T
signals are specified with t
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
1
2
3
TIMING DIAGRAMS
DCLK
1
2
3
4
5
6
7
8
9
Mark/space ratio for the DCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 2.0 V.
t
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
relinquish time of the part and is independent of the bus loading.
A
2
2
3
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown in Figure 3. The measured number is then
= T
1
MIN
to T
MAX
, unless otherwise noted, V
10
20
16
20
20
12
12
16
16
16
0
Limit at T
R
= t
F
MIN
= 5 ns (10% to 90% of V
, T
MAX
DCLK
DOUT
DIN
CS
Figure 3. Load Circuit for Digital Output Timing Specifications
CC
t
6
= 2.7 V to 5.25 V, V
t
MSB
1
1
MSB
TO OUTPUT
Unit
kHz min
MHz max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns min
t
2
Figure 2. Detailed Timing Diagram
4
CC
t
2
PIN
) and timed from a voltage level of 1.6 V.
3
Rev. D | Page 5 of 44
50pF
C
t
t
7
L
5
200µA
200µA
t
REF
3
= 2.5 V. Sample tested at 25°C to ensure compliance. All input
Description
CS falling edge to first DCLK rising edge
DCLK high pulse width
DCLK low pulse width
DIN setup time
DIN hold time
CS falling edge to DOUT, three-state disabled
DCLK falling edge to DOUT valid
CS rising edge to DOUT high impedance
CS rising edge to DCLK ignored
I
I
OL
OH
15
1.6V
16
LSB
LSB
t
t
9
8
8
, quoted in the timing characteristics is the true bus
AD7877