AD7934-6 Analog Devices, AD7934-6 Datasheet - Page 7

• Manufacturer Part Number: AD7934-6
• Description: 4-Channel, 625 kSPS, 12-Bit Parallel ADC with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7934-6

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 625kSPS
• Interface: Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: SOP

AD7934-6
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3 to 10
11
12
13
14 to 16
17
18
19
20
21
Mnemonic
V
W/B
DB0 to DB7
V
DGND
DB8/HBEN
DB9 to DB11
BUSY
CLKIN
CONVST
WR
RD
DD
DRIVE
Description
Power Supply Input. The V
to AGND with a 0.1 μF capacitor and a 10 μF tantalum capacitor.
Word/Byte Input. When this input is logic high, word transfer mode is enabled, and data is transferred to and
from the AD7934-6 in 12-bit words on Pin DB0 to Pin DB11. When W/B is logic low, byte transfer mode is
enabled. Data and the channel ID are transferred on Pin DB0 to Pin DB7, and Pin DB8/HBEN assumes its HBEN
functionality. When operating in byte transfer mode, unused data lines should be tied off to DGND.
Data Bit 0 to Data Bit 7. Three-state parallel digital I/O pins that provide the conversion result, and allow the
control register to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low voltage
levels for these pins are determined by the V
Logic Power Supply Input. The voltage supplied at this pin determines what voltage the parallel interface of
the AD7934-6 operates. This pin should be decoupled to DGND. The voltage at this pin can be different to that
at V
Digital Ground. This is the ground reference point for all digital circuitry on the AD7934-6. This pin should
connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same
potential, and must not be more than 0.3 V apart, even on a transient basis.
Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is
controlled by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low,
the low byte of data written to or read from the AD7934-6 is on DB0 to DB7. When HBEN is high, the top four
bits of the data being written to or read from the AD7934-6 are on DB0 to DB3. When reading from the device,
DB4 and DB5 of the high byte contain the ID of the channel corresponding to the conversion result (see the
channel address bits in Table 9). DB6 and DB7 are always 0. When writing to the device, DB4 to DB7 of the
high byte must all be 0s.
Data Bit 9 to Data Bit 11. Three-state parallel digital I/O pins that provide the conversion result and allow the
control register to be programmed in word mode. These pins are controlled by CS, RD, and WR. The logic
high/low voltage levels for these pins are determined by the V
Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the
falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete
and the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track
mode just prior to the falling edge of BUSY, on the 13
Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the
AD7934-6 takes 13 clock cycles + t
conversion time and achievable throughput rate. The CLKIN signal can be a continuous or burst clock.
Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes
from track to hold mode on the falling edge of CONVST, and the conversion process is initiated at this point.
Following power-down, when operating in the autoshutdown or autostandby mode, a rising edge on
CONVST is used to power up the device.
Write Input. Active low logic input used in conjunction with CS to write data to the control register.
Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion
result is placed on the data bus following the falling edge of RD read while CS is low.
DD
, but should never exceed V
DB8/HBEN
V
DGND
DRIVE
W/B
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB9
V
DD
DD
range for the AD7934-6 is from 2.7 V to 5.25 V. The supply should be decoupled
10
11
12
13
14
1
2
3
4
5
6
7
8
9
Rev. B | Page 7 of 28
(Not to Scale)
AD7934-6
DD
TOP VIEW
2
. The frequency of the master clock input therefore determines the
by more than 0.3 V.
Figure 2.
DRIVE
28
26
25
24
23
22
21
19
18
17
16
15
27
20
V
DB11
V
V
V
V
AGND
CS
RD
WR
CONVST
CLKIN
BUSY
DB10
input.
IN
IN
IN
IN
REFIN
3
2
1
0
th
/V
REFOUT
rising edge of CLKIN (see Figure 34).
DRIVE
input.