AD7746 Analog Devices, AD7746 Datasheet - Page 4

• Manufacturer Part Number: AD7746
• Description: 24-bit, 2 Channel Capacitance to Digital Converter
• Manufacturer: Analog Devices

Specifications of AD7746

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: n/a
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,± 4 pF (Delta C)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7745/AD7746
Parameter
INTERNAL VOLTAGE REFERENCE
EXTERNAL VOLTAGE REFERENCE INPUT
SERIAL INTERFACE LOGIC INPUTS
(SCL, SDA)
OPEN-DRAIN OUTPUT (SDA)
LOGIC OUTPUT ( RDY )
POWER REQUIREMENTS
1
2
3
4
5
6
7
8
9
Capacitance units: 1 pF = 10
Specification is not production tested, but is supported by characterization data at initial product release.
different temperatures, compensation for gain drift over temperature is required.
The capacitive input offset can be eliminated using a system offset calibration. The accuracy of the system offset calibration is limited by the offset calibration register
LSB size (32 aF) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. To minimize the effect of the converter +
system noise, longer conversion times should be used for system capacitive offset calibration. The system capacitance offset calibration range is ±1 pF, the larger
offset can be removed using CAPDACs.
The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required.
further reduce the CIN offset or the unchanging CIN component.
The VTCHOP bit in the VT SETUP register must be set to 1 for the specified temperature sensor and voltage input performance.
Using an external temperature sensing diode 2N3906, with nonideality factor n
Full-scale error applies to both positive and negative full scale.
Factory calibrated. The absolute error includes factory gain calibration error, integral nonlinearity error, and offset error after system offset calibration, all at 25°C. At
The CAPDAC resolution is seven bits in the actual CAPDAC full range. Using the on-chip offset calibration or adjusting the capacitive offset calibration register can
V
Hysteresis
Input Leakage Current (SCL)
V
I
Full-Scale Drift vs. Temperature
Average VIN Input Current
Analog VIN Input Current Drift
Power Supply Rejection
Power Supply Rejection
Normal Mode Rejection
Common-Mode Rejection
Voltage
Drift vs. Temperature
Differential REFIN Voltage
Absolute REFIN Voltage
Average REFIN Input Current
Average REFIN Input Current Drift
Common-Mode Rejection
V
V
V
V
V
V
I
I
OH
DD
DD
IL
OL
IH
OL
OH
OL
OH
DD
Input Low Voltage
Output High Leakage Current
Current
Current Power-Down Mode
Input High Voltage
-to-GND Voltage
Output Low Voltage
Output Low Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
-12
2
F; 1 fF = 10
2
-15
F; 1 aF = 10
Min
1.169
0.1
GND − 0.03
2.1
4.0
V
4.75
2.7
DD
– 0.6
-18
F.
Typ
5
0.5
300
±50
80
90
75
50
95
1.17
5
2.5
400
±50
80
150
±0.1
0.1
750
700
0.5
Rev. 0 | Page 4 of 28
f
= 1.008, connected as in Figure 41, with total serial resistance <100 Ω.
Max
1.171
V
V
0.8
±1
0.4
1
0.4
0.4
5.25
3.6
850
2
DD
DD
+ 0.03
Unit
ppm of FS/°C
ppm of FS/°C
nA/V
pA/V/°C
dB
dB
dB
dB
dB
V
ppm/°C
V
V
nA/V
pA/V/°C
dB
V
V
mV
µA
V
µA
V
V
V
V
V
V
µA
µA
µA
µA
Test Conditions/Comments
Internal reference
External reference
Internal reference, V
External reference, V
50 Hz ± 1%, conversion time = 122.1 ms
60 Hz ± 1%, conversion time = 122.1 ms
V
T
I
V
I
I
I
I
V
V
Digital inputs equal to V
V
V
Digital inputs equal to V
SINK
SINK
SOURCE
SINK
SOURCE
A
IN
OUT
DD
DD
DD
DD
= 25°C
= 1 V
= 5 V, nominal
= 3.3 V, nominal
= 5 V
= 3.3 V
=
= 1.6 mA, V
= 100 µA, V
= V
−
= 200 µA, V
= 100 µA, V
6.0 mA
DD
DD
DD
DD
DD
= 5 V
= 3 V
= 5 V
= 3 V
IN
IN
= V
= V
DD
DD
REF
REF
or GND
or GND
/2
/2