AD7266 Analog Devices, AD7266 Datasheet - Page 20

• Manufacturer Part Number: AD7266
• Description: Differential/Single-Ended Input, Dual, Simultaneous Sampling, 2 MSPS, 12-Bit, 3-Channel SAR A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7266

• Resolution (bits): 12bit
• # Chan: 12
• Sample Rate: 2MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,(Vref) p-p,2.5V p-p,5V p-p,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7266
FULL POWER-DOWN MODE
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes substan-
tially longer than that from partial power-down. This mode is
more suited to applications where a series of conversions
performed at a relatively high throughput rate are followed by a
long period of inactivity and thus power-down. When the
AD7266 is in full power-down, all analog circuitry is powered
down. Full power-down is entered in a similar way as partial
power-down, except the timing sequence shown in Figure 35
must be executed twice. The conversion process must be
interrupted in a similar fashion by bringing CS high anywhere
after the second falling edge of SCLK and before the 10
edge of SCLK. The device enters partial power-down at this
point. To reach full power-down, the next conversion cycle
must be interrupted in the same way, as shown in
Once
completely powers down.
CS is brought high in this window of SCLKs, the part
D
D
D
D
SCLK
SCLK
OUT
OUT
OUT
OUT
CS
CS
A
B
A
B
THE PART BEGINS
TO POWER UP.
1
1
2
INVALID DATA
PARTIAL POWER DOWN.
THE PART ENTERS
INVALID DATA
t
POWER-UP1
Figure 37
Figure 36. Exiting Partial Power-Down Mode
10
Figure 37. Entering Full Power-Down Mode
10
THREE-STATE
th
falling
.
Rev. B | Page 20 of 28
14
14
THE PART BEGINS
TO POWER UP.
Note that it is not necessary to complete the 14 SCLKs once CS
is brought high to enter a power-down mode.
To exit full power-down and power up the AD7266, a dummy
conversion is performed, as when powering up from partial
power-down. On the falling edge of CS , the device begins to
power up and continues to power up, as long as CS is held low
until after the falling edge of the 10
power-up time must elapse before a conversion can be initiated,
as shown in
power-up times associated with the AD7266.
1
2
INVALID DATA
Figure 38
1
THE PART IS FULLY
POWERED UP; SEE
POWER-UP TIMES
SECTION.
FULL POWER DOWN.
THE PART ENTERS
VALID DATA
. See the
Power-Up Times
10
THREE-STATE
14
th
SCLK. The required
14
section for the