AD9219 Analog Devices, AD9219 Datasheet - Page 2

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AD9219

Manufacturer Part Number
AD9219
Description
Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9219

Resolution (bits)
10bit
# Chan
4
Sample Rate
65MSPS
Interface
LVDS,Ser
Analog Input Type
Diff-Uni
Ain Range
(2Vref) p-p,2 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9219BCPZ-65
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9219
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 4
Timing Diagrams .............................................................................. 8
Absolute Maximum Ratings .......................................................... 10
Pin Configuration and Function Descriptions ........................... 11
Equivalent Circuits ......................................................................... 13
Typical Performance Characteristics ........................................... 15
Theory of Operation ...................................................................... 20
REVISION HISTORY
12/11—Rev. D to Rev. E
Added Exposed Pad Notation to Figure 5 ................................... 11
Changes to Output Signals Section and Figure 71 ..................... 37
Change to Default Operation and Jumper Selection Settings
Section .............................................................................................. 38
Change to Figure 74 ....................................................................... 41
Changed LFCSP_WQ to LFCSP_VQ Throughout .................... 53
Added Endnote 2 in Ordering Guide .......................................... 53
5/10—Rev. C to Rev. D
Updated Outline Dimensions ....................................................... 52
Changes to Ordering Guide .......................................................... 52
4/10—Rev. B to Rev. C
Changes to Table 16 ........................................................................ 33
Updated Outline Dimensions ....................................................... 52
7/07—Rev. A to Rev. B
Changes to Figure 2 and Figure 4 ................................................... 7
Changes to Table 17 ........................................................................ 50
AC Specifications .......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Thermal Impedance ................................................................... 10
ESD Caution ................................................................................ 10
Rev. E | Page 2 of 56
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Serial Port Interface (SPI) .............................................................. 31
Memory Map .................................................................................. 33
Evaluation Board ............................................................................ 37
Outline Dimensions ....................................................................... 53
5/07—Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
Changes to Logic Output (SDIO/ODM) Section .......................... 5
Added Endnote 3 to Table 3 ............................................................. 5
Changes to Pipeline Latency ............................................................ 6
Changes to Figure 2 to Figure 4 ....................................................... 7
Changes to Figure 10 ...................................................................... 12
Changes to Figure 15, Figure 23 to Figure 26 Captions ............ 14
Changes to Figure 16, Figure 37, Figure 39, and Figure 40....... 14
Added Figure 46 and Figure 47 .................................................... 20
Change to Figure 50 ....................................................................... 21
Changes to Figure 51 ...................................................................... 21
Changes to Clock Duty Cycle Considerations Section ............. 22
Changes to Power Dissipation and
Power-Down Mode Section .......................................................... 23
Changes to Figure 58 ...................................................................... 23
Changes to Figure 61 to Figure 63 Captions ............................... 25
Change to Table 8 ........................................................................... 25
Changes to Digital Outputs and Timing Section ....................... 26
Changes to Table 9 Endnote .......................................................... 26
Added Table 10 ............................................................................... 27
Deleted Figure 62 and Figure 63 .................................................. 27
Analog Input Considerations ................................................... 20
Clock Input Considerations ...................................................... 23
Hardware Interface ..................................................................... 31
Reading the Memory Map Table .............................................. 33
Reserved Locations .................................................................... 33
Default Values ............................................................................. 33
Logic Levels ................................................................................. 33
Power Supplies ............................................................................ 37
Input Signals................................................................................ 37
Output Signals ............................................................................ 37
Default Operation and Jumper Selection Settings ................. 38
Alternative Analog Input Drive Configuration...................... 39
Ordering Guide .......................................................................... 53
Data Sheet
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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