AD7657 Analog Devices, AD7657 Datasheet
AD7657
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AD7657 Summary of contents
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... ADCs to connect to a single serial interface. The AD7656/ AD7657/AD7658 can accommodate true bipolar input signals in the ±4 × V range and ±2 × V REF AD7657/AD7658 also contain an on-chip 2.5 V reference. PRODUCT HIGHLIGHTS 1. Six 16-/14-/12-bit, 250 kSPS ADCs on board. 2. Six true bipolar, high impedance analog inputs. ...
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... ADC Transfer Function ............................................................. 21 Reference Section ....................................................................... 21 Typical Connection Diagram ................................................... 21 Driving the Analog Inputs ........................................................ 22 Interface Section ......................................................................... 22 Application Hints ........................................................................... 29 Layout .......................................................................................... 29 Power Supply Configuration .................................................... 29 Outline Dimensions ....................................................................... 30 Ordering Guide .......................................................................... 30 4/06—Rev Rev. A Added AD7657/AD7658 parts ......................................... Universal Changes to Table 1 ............................................................................. 3 Changes to Table 5 .......................................................................... 10 3/06—Revision 0: Initial Version Rev Page ...
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... V min/max 150 150 ppm typ 25 25 ppm/°C max 6 6 ppm/°C typ Rev Page AD7656/AD7657/AD7658 = 2 5.25 V; DRIVE = 16 − −16 Test Conditions/Comments kHz sine wave ± ± ± ...
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... AD7656/AD7657/AD7658 Parameter LOGIC INPUTS Input High Voltage (V ) INH Input Low Voltage (V ) INL Input Current ( Input Capacitance ( LOGIC OUTPUTS Output High Voltage ( Output Low Voltage ( Floating-State Leakage Current 3 Floating-State Output Capacitance Output Coding CONVERSION RATE Conversion Time 2, 3 Track-and-Hold Acquisition Time ...
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... DRIVE 0.3 × V 0.3 × max DRIVE DRIVE ±1 ±1 μA max max Rev Page AD7656/AD7657/AD7658 = 2 5.25 V; DRIVE = 16 − −16 Test Conditions/Comments kHz sine wave kHz kHz f on unselected channels up to 100 kHz IN @ − ...
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... AD7656/AD7657/AD7658 Parameter LOGIC OUTPUTS Output High Voltage ( Output Low Voltage ( Floating-State Leakage Current Floating-State Output Capacitance 3 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time 2, 3 Throughput Rate POWER REQUIREMENTS DRIVE I TOTAL Normal Mode (Static) ...
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... DRIVE 0.3 × V 0.3 × max DRIVE DRIVE ±1 ±1 μA max max Rev Page AD7656/AD7657/AD7658 = 2 5.25 V; DRIVE = 16 − −16 Test Conditions/Comments kHz sine wave kHz kHz f on unselected channels up to 100 kHz IN @ − ...
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... AD7656/AD7657/AD7658 Parameter LOGIC OUTPUTS Output High Voltage ( Output Low Voltage ( Floating-State Leakage Current Floating-State Output Capacitance 3 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time 2, 3 Throughput Rate POWER REQUIREMENTS DRIVE I TOTAL Normal Mode (Static) ...
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... C L 25pF 200µ Figure 2. Load Circuit for Digital Output Timing Specification Rev Page AD7656/AD7657/AD7658 = 2.5 V internal/external, REF Description Conversion time, internal clock Minimum quiet time required between bus relinquish and start of next conversion Acquisition time Minimum CONVST low pulse ...
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... AD7656/AD7657/AD7658 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 5. Parameter V to AGND, DGND AGND, DGND AGND, DGND DGND, AGND CC AGND to DGND V to DGND DRIVE 1 Analog Input Voltage to AGND Digital Input Voltage to DGND ...
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... Nominally at the same supply as the supply of the host interface. This pin should be decoupled to DGND, and 10 μF and 100 nF decoupling capacitors should be placed on the V Digital Ground. This is the ground reference point for all digital circuitry on the AD7656/AD7657/AD7658. Both DGND pins should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0 ...
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... BUSY Output. This pin transitions high when a conversion is started and remains high until the conversion is complete and the conversion data is latched into the output data registers. A new conversion should not be initiated on the AD7656/AD7657/AD7658 when the BUSY signal is high. Reference Input/Output. The on-chip reference is available on this pin for use external to the AD7656/AD7657/AD7658 ...
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... When CS and RD are low, these pins are used to output the conversion result. When CS and WR are low, these pins are used to write to the control register. When SER/PAR = 1, these pins should be tied to DGND. For the AD7657, DB15 contains a leading zero. For the AD7658, DB15, DB13, and DB12 contain leading zeros. ...
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... CODE Figure 8. AD7657 Typical INL 2 DRIVE ±12V 1 1.2 0.8 0.4 0 –0.4 –0.8 –1.2 –1.6 –2.0 0 2000 4000 6000 8000 10000 12000 14000 16383 CODE Figure 9. AD7657 Typical DNL 60k 65535 /V = +5V DRIVE ...
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... +5V –60 DRIVE /V = ±12V DD SS –70 –80 –90 –100 –110 –120 1000 10 Figure 15. AD7656 THD vs. Input Frequency for Various Source Impedances, Rev Page AD7656/AD7657/AD7658 f = 250kSPS SAMPLE INTERNAL REFERENCE T = 25° / + DRIVE ±5.25V DD SS ±5V RANGE ...
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... AD7656/AD7657/AD7658 2.510 DRIVE ±12V DD SS 2.508 2.506 2.504 2.502 2.500 2.498 2.496 2.494 2.492 –55 –35 – TEMPERATURE (°C) Figure 16. Reference Voltage vs. Temperature 3.20 3.15 3.10 3.05 3.00 2.95 2.90 2.85 2.80 2.75 2.70 –55 –35 – TEMPERATURE (°C) Figure 17. Conversion Time vs. Temperature 3500 3212 3000 ...
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... FREQUENCY OF INPUT NOISE (kHz) Figure 22. Channel-to-Channel Isolation 120 140 –40 Rev Page AD7656/AD7657/AD7658 ±10V RANGE ±5V RANGE DRIVE f = 250kSPS SAMPLE FOR ±5V RANGE ±12V DD SS FOR ±10V RANGE ± ...
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... The AD7656/AD7657/AD7658 are tested using the CCIF standard in which two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are ...
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... Figure 19 shows the power supply rejection ratio vs. supply ripple frequency for the AD7656/AD7657/AD7658. The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency the power of a 200 mV p-p sine wave applied to the ADC’s V and V supplies of frequency f ...
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... RANGE pin/RNGx bit is 0, the analog input range for the next conversion is ±4 × V Figure 24 shows an equivalent circuit of the analog input structure of the AD7656/AD7657/AD7658. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the ...
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... The three internal reference buffers are enabled. Each of the REFCAP pins are decoupled with the 10 μF and 100 nF capacitor pair. Six of the AV ADC cores on the AD7656/AD7657/AD7658 and result, are used for the conversion process. Each analog input pin is surrounded ...
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... The AD7656/AD7657/AD7658 consist of six 16-/14-/12-bit ADCs, respectively. A simultaneous sample of all six ADCs can be performed by connecting all three CONVST pins together, CONVST A, CONVST B, and CONVST C. The AD7656/AD7657/ AD7658 need to see a CONVST pulse to initiate a conversion; this should consist of a falling CONVST edge followed by a rising CONVST edge ...
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... V1, V2, V5, and V6. The conversion results are output in ascending order. For the AD7657, DB15 and DB14 contain two leading zeros and DB[13:0] output the 14-bit conversion result. For the AD7658, DB[15:12] contain four leading zeros, and DB[11:0] output the 12-bit conversion result ...
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... ADC pair. DB12 to DB10 in the control register are used to program the range on each ADC pair. After a reset occurs on the AD7656/AD7657/AD7658, the control register contains all zeros. The CONVST A signal is used to initiate a simultaneous conversion on the combination of channels selected via the control register ...
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... AD7656 consists of 16 bits of conversion data provided MSB first. The data stream for the AD7657 consists of two leading zeros followed by 14 bits of conversion data MSB first. The data stream for the AD7658 consists of four leading zeros and 12 bits of conversion data provided MSB first ...
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... AD7656/AD7657/AD7658 CONVST A, CONVST B, CONVST C BUSY CS SCLK DOUT A DOUT B DOUT C CS SCLK DOUT A DOUT CONVST A, CONVST B, t CONVERT CONVST C t BUSY ACQUISITION CONVERSION CS SCLK DOUT A, DOUT B, DOUT CONVERT ACQ Figure 30. Serial Interface with Three DOUT Lines Figure 31 ...
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... AD7656/AD7657/ D7658 devices in daisy-chain mode. The CS falling edge is used to frame the serial transfer from the AD7656/AD7657/AD7658 devices, to take the bus out of three- state, and to clock out the MSB of the first conversion result. In the example shown in ...
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... MSB V1 DEVICE 1, DOUT B MSB V3 DEVICE 1, DOUT C MSB V5 DEVICE 2, DOUT A MSB V1 DEVICE 2, DOUT B MSB V3 DEVICE 2, DOUT C MSB V5 CONVST DOUT A DCIN A DOUT A DCIN B DOUT B DOUT B AD7656/AD7657/AD7658 CS SCLK CS DCEN = 1 DEVICE 1 Figure 33. Daisy-Chain Configuration LSB V1 MSB V2 LSB V2 MSB V5 LSB V3 MSB V4 LSB V4 MSB V6 ...
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... AD7657/AD7658 pin configuration easily facilitates this. For the AD7656, decouple each pair with a 100 μF capacitor; for the AD7657, decouple each pair with a 33 μF capacitor; for the AD7658, decouple each pair with a 22 μF capacitor. For this minimum decoupling configuration, all other supply and reference pins should be decoupled with a 10 μ ...
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... The EVAL-CONTROL BRD2Z is a complete unit allowing control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, the particular ADC evaluation board, for example, EVAL-AD7656/AD7657/AD7658CBZ, the EVAL-CONTROL BRD2Z and transformer must be ordered. See the relevant evaluation board technical note for more information. ...
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... NOTES AD7656/AD7657/AD7658 Rev Page ...
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... AD7656/AD7657/AD7658 NOTES ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05020-0-8/10(C) Rev Page ...