AD9287 Analog Devices, AD9287 Datasheet - Page 19

• Manufacturer Part Number: AD9287
• Description: Quad, 8-Bit, 100 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9287

• Resolution (bits): 8bit
• # Chan: 4
• Sample Rate: 100MSPS
• Interface: LVDS,Ser
• Analog Input Type: Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Data Sheet
THEORY OF OPERATION
The AD9287 architecture consists of a pipelined ADC divided into
three sections: a 4-bit first stage followed by eight 1.5-bit stages and
a final 3-bit flash. Each stage provides sufficient overlap to correct
for flash errors in the preceding stage. The quantized outputs from
each stage are combined into a final 8-bit result in the digital
correction logic. The pipelined architecture permits the first stage
to operate with a new input sample while the remaining stages
operate with preceding samples. Sampling occurs on the rising
edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction of
flash errors. The last stage simply consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and data clocks.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9287 is a differential switched-
capacitor circuit designed for processing differential input
signals. The circuit can support a wide common-mode range
while maintaining excellent performance. By using an input
common-mode voltage of midsupply, users can minimize
signal-dependent errors and achieve optimum performance.
The clock signal alternately switches the input circuit between
sample mode and hold mode (see Figure 35). When the input
circuit is switched to sample mode, the signal source must be
capable of charging the sample capacitors and settling within
one-half of a clock cycle. A small resistor in series with each
input can help reduce the peak transient current injected from
the output stage of the driving source. In addition, low-Q inductors
or ferrite beads can be placed on each leg of the input to reduce
high differential capacitance at the analog inputs and therefore
achieve the maximum bandwidth of the ADC. Such use of low-Q
VIN + x
VIN – x
Figure 35. Switched-Capacitor Input Circuit
C
C
PAR
PAR
H
H
S
S
C
C
SAMPLE
SAMPLE
S
S
H
H
Rev. E | Page 19 of 52
inductors or ferrite beads is required when driving the converter
front end at high IF frequencies. Either a shunt capacitor or two
single-ended capacitors can be placed on the inputs to provide a
matching passive network. This ultimately creates a low-pass
filter at the input to limit unwanted broadband noise. See the
AN-742 Application Note, the AN-827 Application Note, and the
Analog Dialogue article “Transformer-Coupled Front-End for
Wideband A/D Converters” (Volume 39, April 2005) for more
information at www.analog.com. In general, the precise values
depend on the application.
The analog inputs of the AD9287 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide
this bias externally. Setting the device so that V
recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 36 and Figure 37.
90
80
70
60
50
40
30
20
10
90
80
70
60
50
40
30
20
10
0
0
0.2
0.2
f
f
f
f
IN
SAMPLE
IN
SAMPLE
Figure 36. SNR/SFDR vs. Common-Mode Voltage,
Figure 37. SNR/SFDR vs. Common-Mode Voltage,
= 2.4MHz
= 30MHz
0.4
0.4
ANALOG INPUT COMMON-MODE VOLTAGE (V)
ANALOG INPUT COMMON-MODE VOLTAGE (V)
= 100MSPS
= 100MSPS
f
f
IN
IN
= 2.4 MHz, f
= 30 MHz, f
0.6
0.6
0.8
0.8
SAMPLE
SAMPLE
SFDR (dBc)
SNR (dB)
SFDR (dBc)
SNR (dB)
= 100 MSPS
= 100 MSPS
1.0
1.0
1.2
1.2
CM
1.4
1.4
= AVDD/2 is
AD9287
1.6
1.6