AD9252 Analog Devices, AD9252 Datasheet - Page 31

• Manufacturer Part Number: AD9252
• Description: Octal, 14-Bit, 50 MSPS, Serial LVDS, 1.8 V ADC
• Manufacturer: Analog Devices

Specifications of AD9252

• Resolution (bits): 14bit
• # Chan: 8
• Sample Rate: 50MSPS
• Interface: LVDS,Ser
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Data Sheet
Addr.
(Hex)
14
15
16
19
1A
1B
1C
21
22
1
X = an undefined feature.
Parameter Name
output_mode
output_adjust
output_phase
user_patt1_lsb
user_patt1_msb
user_patt2_lsb
user_patt2_msb
serial_control
serial_ch_stat
(MSB)
Bit 7
X
X
X
B7
B15
B7
B15
LSB first
1 = on
0 = off
(default)
X
Bit 6
0 = LVDS
ANSI-644
(default)
1 = LVDS
low power,
(IEEE 1596.3
similar)
X
X
B6
B14
B6
B14
X
X
Bit 5
X
Output driver
termination
00 = none (default)
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
X
B5
B13
B5
B13
X
X
Bit 4
X
X
B4
B12
B4
B12
X
X
Rev. E | Page 31 of 52
Bit 3
X
X
0011 = output clock phase adjust
(0000 through 1010)
0000 = 0° relative to data edge
0001 = 60° relative to data edge
0010 = 120° relative to data edge
0011 = 180° relative to data edge (default)
0101 = 300° relative to data edge
0110 = 360° relative to data edge
1000 = 480° relative to data edge
1001 = 540° relative to data edge
1010 = 600° relative to data edge
1011 to 1111 = 660° relative to data edge
B3
B11
B3
B11
<10
MSPS,
low
encode
rate
mode
1 = on
0 = off
(default)
X
Bit 2
Output
invert
1 = on
0 = off
(default)
X
B2
B10
B2
B10
000 = 14 bits (default, normal bit
stream)
001 = 8 bits
010 = 10 bits
011 = 12 bits
100 = 14 bits
X
Bit 1
00 = offset binary
(default)
01 = twos complement
X
B1
B9
B1
B9
Channel
output
reset
1 = on
0 = off
(default)
(LSB)
Bit 0
DCO and
FCO
2× drive
strength
1 = on
0 = off
(default)
B0
B8
B0
B8
Channel
power-
down
1 = on
0 = off
(default)
Default
Value
(Hex)
0x00
0x00
0x03
0x00
0x00
0x00
0x00
0x00
0x00
Notes/
Comments
Configures the
outputs and the
format of the data.
Determines
LVDS or other
output properties.
Primarily func-
tions to set the
LVDS span and
common-mode
levels in place of
an external
resistor.
On devices that
utilize global
clock divide,
this register
determines
which phase
of the divider
output is used
to supply the
output clock.
Internal latching
is unaffected.
User-defined
pattern, 1 LSB.
User-defined
pattern, 1 MSB.
User-defined
pattern, 2 LSB.
User-defined
pattern, 2 MSB.
Serial stream
control. Default
causes MSB first
and the native
bit stream
(global).
Used to power
down individual
sections of a
converter (local).
AD9252