AD7610 Analog Devices, AD7610 Datasheet - Page 6

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AD7610

Manufacturer Part Number
AD7610
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD7610

Resolution (bits)
16bit
# Chan
1
Sample Rate
250kSPS
Interface
Par,Ser,SPI
Analog Input Type
SE-Bip,SE-Uni
Ain Range
Bip 10V,Bip 5.0V,Uni 10V,Uni 5.0V
Adc Architecture
SAR
Pkg Type
CSP,QFP

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AD7610
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
DIVSCLK[0]
SYNC to SDCLK First Edge Delay Minimum
Internal SDCLK Period Minimum
Internal SDCLK Period Maximum
Internal SDCLK High Minimum
Internal SDCLK Low Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SDCLK Last Edge to SYNC Delay Minimum
BUSY High Width Maximum
TO OUTPUT
NOTES
1. IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT ARE DEFINED WITH A MAXIMUM LOAD
C
L
Figure 2. Load Circuit for Digital Interface Timing,
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
SDOUT, SYNC, and SCLK Outputs, C
PIN
60pF
C
L
1.6mA
500µA
I
I
OL
OH
1.4V
L
= 10 pF
Rev. 0 | Page 6 of 32
Symbol
t
t
t
t
t
t
t
t
t
18
19
19
20
21
22
23
24
28
t
DELAY
0.8V
0
0
3
30
45
15
10
4
5
5
2.25
Figure 3. Voltage Reference Levels for Timing
2V
0.8V
0
1
20
60
90
30
25
20
8
7
3.00
1
0
20
120
180
60
55
20
35
35
4.40
2V
t
2V
0.8V
DELAY
1
1
20
240
360
120
115
20
90
90
7.30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs

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