AD7693 Analog Devices, AD7693 Datasheet - Page 22

• Manufacturer Part Number: AD7693
• Manufacturer: Analog Devices

Specifications of AD7693

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,Bip (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7693
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7693s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications
or for systems with a limited interfacing capacity. Data readback
is analogous to clocking a shift register.
A connection diagram example using three AD7693s is shown
in Figure 44, and the corresponding timing is given in Figure 45.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
ACQUISITION
SDO
SDO
CNV = SDI
t
HSCKCNV
A
B
SCK
= SDI
= SDI
SDO
A
B
C
C
SDI
CONVERSION
t
t
DSDOSDI
t
SSCKCNV
t
CONV
DSDOSDI
AD7693
t
EN
CNV
SCK
A
SDO
t
t
t
SSDISCK
HSDO
DSDO
1
D
D
D
C
A
B
2
15 D
15 D
15 D
Figure 45. Chain Mode with Busy Indicator Serial Interface Timing
Figure 44. Chain Mode with Busy Indicator Connection Diagram
C
A
B
3
14 D
14 D
14 D
t
SCKH
SDI
C
A
B
t
4
HSDISCK
13
13
13
AD7693
CNV
SCK
B
15
t
SCK
Rev. A | Page 22 of 24
D
D
D
16
SDO
C
B
A
1
1
1
t
SCKL
D
D
D
17
C
A
B
0
0 D
0
D
ACQUISITION
18
B
A
15 D
15 D
t
CYC
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7693 ADC labeled C in Figure 44) is
driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7693 then enters the acquisition phase and powers
down. The data bits stored in the internal shift register are
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N + 1 clocks are required to
readback the N ADCs. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate and consequently more AD7693s in the
chain, provided the digital host has an acceptable hold time.
19
B
A
SDI
t
14
14
ACQ
AD7693
CNV
SCK
31
C
D
D
32
B
A
SDO
1
1
D
D
33
B
A
0 D
0
34
A
15
D
35
A
14
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
47
t
DSDOSDI
D
48
t
A
DSDOSDI
t
1
DSDOSDI
D
49
A
0