AD9640 Analog Devices, AD9640 Datasheet - Page 34

• Manufacturer Part Number: AD9640
• Description: 14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9640

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 150MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9640
similarly, corresponds to the fine lower threshold bits, except
that it is asserted only if the input magnitude is less than the
value programmed in the fine lower threshold register after the
dwell time elapses. The dwell time is set by the 16-bit dwell time
value located at Address 0x10A and Address 0x10B and is set in
units of ADC input clock cycles ranging from 1 to 65,535. The
fine lower threshold register is a 13-bit register that is compared
with the magnitude at the output of the ADC. This comparison
is subject to the ADC clock latency but allows a finer, more
accurate comparison. The fine upper threshold magnitude is
defined by the following equation:
F_UT
F_LT
Figure 67. Threshold Settings for F_UT and F_LT
Rev. B | Page 34 of 52
The decrement gain output works from the ADC fast detect
output pins, providing a fast indication of potential overrange
conditions. The increment gain uses the comparison at the
output of the ADC, requiring the input magnitude to remain
below an accurate, programmable level for a predefined period
before signaling external circuitry to increase the gain.
The operation of the increment gain output and the decrement
gain output is shown in Figure 67.
dBFS = 20 log(Threshold Magnitude/2
FINE LOWER THRESHOLD
FINE UPPER THRESHOLD
13
)