AD7980 Analog Devices, AD7980 Datasheet - Page 20

• Manufacturer Part Number: AD7980
• Manufacturer: Analog Devices

Specifications of AD7980

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7980
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7980 is connected
to an SPI-compatible digital host that has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the
data reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 37, and the
corresponding timing is given in Figure 38.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high impedance
to low.
AQUISITION
CNV
SCK
SDO
t
SDI
SSDICNV
t
HSDICNV
CONVERSION
Figure 38. 4-Wire CS Mode with Busy Indicator Serial Interface Timing
t
CONV
t
EN
Rev. B | Page 20 of 28
1
t
HSDO
D15
2
t
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data readback controlled by
the digital host. The AD7980 then enters the acquisition phase
and powers down. The data bits are clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge or SDI going high, whichever is earlier,
the SDO returns to high impedance.
CYC
D14
3
t
Figure 37. 4-Wire CS Mode with Busy Indicator Connection Diagram
DSDO
AQUISITION
t
ACQ
t
SCKL
SDI
15
t
SCKH
AD7980
CNV
SCK
t
SCK
16
D1
SDO
17
D0
VIO
47kΩ
t
DIS
CS1
CONVERT
DATA IN
IRQ
CLK
DIGITAL HOST