AD7366 Analog Devices, AD7366 Datasheet - Page 22

• Manufacturer Part Number: AD7366
• Description: True Bipolar Input, Dual 12-Bit, 2-Channel, Simultaneous Sampling SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7366

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip (Vref) x 2,Bip (Vref) x 4,Bip 10V,Bip 5.0V,Uni (Vref) x 4,Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

AD7366/AD7367
SERIAL INTERFACE
Figure 25 and Figure 26 show the detailed timing diagram for
serial interfacing to the AD7366 and the AD7367. On the
falling edge of CNVST , the AD7366/AD7367 simultaneously
convert the selected channels. These conversions are performed
using the on-chip oscillator. After the falling edge of CNVST
the BUSY signal goes high, indicating that the conversion has
started. The BUSY signal returns low when the conversion has
been completed. The data can now be read from the
The CS and SCLK signals are required to transfer data from the
AD7366/AD7367. The AD7366/AD7367 have two output pins
corresponding to each ADC. Data can be read from the AD7366/
AD7367 using both D
output pin of the user’s choice can be used. The SCLK input
signal provides the clock source for the serial interface. The CS
goes low to access data from the AD7366/AD7367. The falling
edge of CS takes the bus out of three-state and clocks out the
MSB of the conversion result. The data stream consists of
12 bits of data for the AD7366 and 14 bits of data for the
AD7367, MSB first. The first bit of the conversion result is
valid on the first SCLK falling edge after the CS falling edge.
The subsequent 11/13 bits of data for the AD7366/AD7367,
respectively, are clocked out on the falling edge of the SCLK
signal. A minimum of 12 clock pulses must be provided to the
AD7366 to access each conversion result, and a minimum of
14 clock pulses must be provided to the AD7367 to access the
conversion result. Figure 25 shows how a 12 SCLK read is used
to access the conversion results for the AD7366, and Figure 26
illustrates the case for the AD7367 with a 14 SCLK read.
D
D
D
D
SCLK
OUT
OUT
SCLK
OUT
OUT
CS
CS
A
B
A
B THREE-
THREE-
STATE
STATE
OUT
DB11
DB13
A and D
1
1
t
t
4
4
DB10
DB12
OUT
2
2
DB11
B. Alternatively, a single
DB9
3
3
DB10
Figure 25. Serial Interface Timing Diagram for the AD7366
Figure 26. Serial Interface Timing Diagram for the AD7367
DB8
4
4
D
t
t
OUT
5
5
t
t
8
8
pins.
5
5
Rev. D | Page 22 of 28
,
t
t
6
6
On the rising edge of CS the conversion is terminated and
D
high, but is instead held low for an additional 14 SCLK cycles
the data from the other DOUT pin follows on the selected
DOUT pin. Note, the second serial result from the AD7366 is
preceeded by two zeros. See Figure 27
D
three-state on the rising edge of CS .
If the falling edge of SCLK coincides with the falling edge of CS ,
the falling edge of SCLK is not acknowledged by the AD7366/
AD7367, and the next falling edge of SCLK is the first one
registered after the falling edge of CS .
The CS pin can be brought low before the BUSY signal goes
low, indicating the end of a conversion. When CS is at a logic
low state, the data bus is brought out of three-state. This feature
can be used to ensure that the MSB is valid on the falling edge
of BUSY by bringing CS low a minimum of t
signal goes low. The dotted CS
illustrates this feature.
Alternatively, the CS pin can be tied to a low logic state continu-
ously. In this case, the D
data bus is continuously active. Under these conditions, the MSB
of the conversion result for the AD7366/AD7367 is available on
the falling edge of the BUSY signal. The next most significant
bit is available on the first SCLK falling edge after the BUSY
signal has gone low. This mode of operation enables the user to
read the MSB as soon as it is made available by the converter.
OUT
OUT
A and D
A is shown. In this case, the D
DB2
DB2
t
t
7
7
OUT
DB1
DB1
B return to three-state. If CS is not brought
DB0
DB0
OUT
t
t
9
9
pins never enter three-state and the
14
12
line in Figure 22 and Figure 23
THREE-STATE
THREE-STATE
OUT
and
line in use returns to
Figure 28, where
4
before the BUSY