AD7699 Analog Devices, AD7699 Datasheet - Page 13

• Manufacturer Part Number: AD7699
• Description: 16-Bit, 8-Channel, 500 kSPS PulSAR ADC
• Manufacturer: Analog Devices

Specifications of AD7699

• Resolution (bits): 16bit
• # Chan: 8
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Bip,SE-Uni
• Ain Range: (Vref) p-p,4 V p-p,Bip (Vref) x 0.5,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP

Data Sheet
THEORY OF OPERATION
OVERVIEW
The
successive approximation register (SAR) analog-to-digital
converter (ADC). It is capable of converting 500,000 samples
per second (500 kSPS) and power down between conversions.
For example, when operating with an external reference at
1 kSPS, it consumes 52 μW typically, ideal for battery-powered
applications.
The
multichannel, low power data acquisition system, including
•
•
•
•
•
•
These components are configured through an SPI-compatible,
14-bit register. Conversion results, also SPI compatible, can be
read after or during conversions with the option for reading
back the configuration.
The
and does not exhibit pipeline delay or latency.
The
to any 1.8 V to 5 V digital logic family. It is housed in a 20-lead,
4 mm × 4 mm LFCSP that combines space savings and allows
flexible configurations and is also pin-for-pin compatible with
the 16-bit
AD7699
AD7699
AD7699
AD7699
16-bit SAR ADC with no missing codes
8-channel, low crosstalk multiplexer
Internal low drift reference and buffer
Temperature sensor
Selectable one-pole filter
Channel sequencer
INx– OR
COM
INx+
GND
REF
AD7682
is specified from 4.5 V to 5.5 V and can be interfaced
is an 8-channel, 16-bit, charge redistribution
contains all of the components for use in a
provides the user with an on-chip track-and-hold
and
AD7689,
and the 14-bit AD7949.
32,768C
32,768C
16,384C
16,384C
MSB
MSB
Figure 25. ADC Simplified Schematic
4C
4C
Rev. A | Page 13 of 28
2C
2C
CONVERTER OPERATION
The
charge redistribution DAC. Figure 25 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary-weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator input are connected to GND via SW+ and SW−. All
independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the INx+ and INx− (or COM)
inputs. When the acquisition phase is complete and the CNV
input goes high, a conversion phase is initiated. When the
conversion phase begins, SW+ and SW− are opened first. The
two capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the INx+ and INx− (or COM) inputs captured at the
end of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between GND and REF, the
comparator input varies by binary-weighted voltage steps
(V
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase, and the control logic
generates the ADC output code and a busy signal indicator.
Because the
serial clock, SCK, is not required for the conversion process.
C
C
REF
AD7699
/2, V
C
C
REF
LSB
LSB
AD7699
/4, ... V
is a successive approximation ADC based on a
SW+
SW–
REF
COMP
has an on-board conversion clock, the
/32,768). The control logic toggles these
SWITCHES CONTROL
CONTROL
LOGIC
CNV
BUSY
OUTPUT CODE
AD7699