AD9258 Analog Devices, AD9258 Datasheet - Page 40

• Manufacturer Part Number: AD9258
• Description: 14-Bit, 125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9258

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 125MSPS
• Interface: Par
• Analog Input Type: Diff-Bip
• Ain Range: (2Vref) p-p,1 V p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9258
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x100)
Bits[7:3]—Reserved
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Address 0x100, Bit0) and the clock
divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2 allows
the clock divider to sync to the first sync pulse it receives and to
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ignore the rest. The clock divider sync enable bit (Address 0x100,
Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions. If the
sync capability is not used this bit should remain low to
conserve power.